Npcm main - James' commits in an archive

boards/nuvoton/npcm400f_evb/doc/index.rst

@@ -0,0 +1,99 @@
+.. _npcm400f_evb:
+
+Nuvoton NPCM400F_EVB
+####################
+
+Overview
+********
+
+The NPCX400F_EVB kit is a development platform to evaluate the
+Nuvoton NPCM4 series microcontrollers. This board needs to be mated with
+part number NPCM400F.
+
+.. image:: npcm400f_evb.jpg
+     :align: center
+     :alt: NPCM400F Evaluation Board
+
+Hardware
+********
+
+- ARM Cortex-M4F Processor
+- 768 KB RAM and 64 KB boot ROM
+- ADC & GPIO headers
+- UART0 and UART1
+
+Supported Features
+==================
+
+The following features are supported:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| ADC       | on-chip    | adc controller                      |
++-----------+------------+-------------------------------------+
+| CLOCK     | on-chip    | reset and clock control             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c port/controller                 |
++-----------+------------+-------------------------------------+
+| I3C       | on-chip    | i3c port/controller                 |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| WDT       | on-chip    | watchdog                            |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+:zephyr_file:`boards/nuvoton/npcm400f_evb/npcm400f_evb_defconfig`
+
+
+Connections and IOs
+===================
+
+Nuvoton to provide the schematic for this board.
+
+System Clock
+============
+
+The NPCX400F MCU is configured to use the 96Mhz.
+
+Serial Port
+===========
+
+UART0 is configured for serial logs.
+
+Programming and Debugging
+*************************
+
+This board comes with a Cortex ETM port which facilitates tracing and debugging
+using a single physical connection. In addition, it comes with sockets for
+JTAG-only sessions.
+
+Flashing
+========
+
+If the correct headers are installed, this board supports J-TAG.
+
+To flash with J-TAG, install the drivers for your programmer, for example:
+SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/
+
+Build and flash the shell module sample.::
+
+  west build -t clean && \
+    west build -c -p auto -b npcm400f_evb samples/subsys/shell/shell_module/ && \
+    west flash --openocd /usr/local/bin/openocd
+
+Debugging
+=========
+
+Use JTAG/SWD with a J-Link
+
+References
+**********

boards/nuvoton/npcm400f_evb/npcm400f_evb.dts

@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <nuvoton/npcm400f.dtsi>
+#include <nuvoton/npcm/npcm4/npcm4-pinctrl.dtsi>
 
 / {
 	model = "Nuvoton NPCM400F evaluation board";
@@ -18,5 +19,4 @@
 
 	aliases {
 	};
-
 };

boards/nuvoton/npcm400f_evb/npcm400f_evb_defconfig

@@ -8,8 +8,18 @@ CONFIG_SRAM_VECTOR_TABLE=y
 CONFIG_BOOTLOADER_SRAM_SIZE=0
 # General Kernel Options
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
+# CONFIG_FLASH_LOAD_OFFSET=0x600
 CONFIG_XIP=n
 
+# CONFIG_ARM_MPU=y
+
+# Clock Driver
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_NPCM=y
+
+# Pinctrl Driver
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_NPCM=y
 
 # UART Driver
 CONFIG_SERIAL=n
@@ -18,3 +28,7 @@ CONFIG_SERIAL=n
 # Console Driver
 CONFIG_CONSOLE=n
 CONFIG_UART_CONSOLE=n
+
+# GPIO Driver
+CONFIG_GPIO=y
+CONFIG_GPIO_NPCM=y

drivers/clock_control/CMakeLists.txt

@@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_PCC            clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG            clock_control_mcux_scg.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM            clock_control_mcux_sim.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SYSCON         clock_control_mcux_syscon.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCM                clock_control_npcm.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCX                clock_control_npcx.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF                 clock_control_nrf.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)

drivers/clock_control/Kconfig

@@ -50,6 +50,8 @@ source "drivers/clock_control/Kconfig.mcux_sim"
 
 source "drivers/clock_control/Kconfig.mcux_syscon"
 
+source "drivers/clock_control/Kconfig.npcm"
+
 source "drivers/clock_control/Kconfig.npcx"
 
 source "drivers/clock_control/Kconfig.rv32m1"

drivers/clock_control/Kconfig.npcm

@@ -0,0 +1,11 @@
+# NPCM Clock controller driver configuration options
+
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_NPCM
+	bool "NPCM clock controller driver"
+	default y
+	depends on DT_HAS_NUVOTON_NPCM_PCC_ENABLED
+	help
+	  Enable support for NPCM clock controller driver.

drivers/clock_control/clock_control_npcm.c

@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nuvoton_npcm_pcc
+
+#include <soc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/clock/npcm_clock.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(clock_control_npcm, LOG_LEVEL_ERR);
+
+/* Driver config */
+struct npcm_pcc_config {
+	/* cdcg device base address */
+	uintptr_t base_cdcg;
+	/* pmc device base address */
+	uintptr_t base_pmc;
+};
+
+/* Driver convenience defines */
+#define DRV_CONFIG(dev) \
+	((const struct npcm_pcc_config *)(dev)->config)
+
+#define HAL_CDCG_INST(dev) \
+	(struct cdcg_reg *)(DRV_CONFIG(dev)->base_cdcg)
+
+/* Clock controller local functions */
+static inline int npcm_clock_control_on(const struct device *dev,
+					 clock_control_subsys_t sub_system)
+{
+	ARG_UNUSED(dev);
+	struct npcm_clk_cfg *clk_cfg = (struct npcm_clk_cfg *)(sub_system);
+	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
+
+	if (clk_cfg->ctrl >= NPCM_PWDWN_CTL_COUNT)
+		return -EINVAL;
+
+	/* Clear related PD (Power-Down) bit of module to turn on clock */
+	NPCM_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit));
+	return 0;
+}
+
+static inline int npcm_clock_control_off(const struct device *dev,
+					  clock_control_subsys_t sub_system)
+{
+	ARG_UNUSED(dev);
+	struct npcm_clk_cfg *clk_cfg = (struct npcm_clk_cfg *)(sub_system);
+	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
+
+	if (clk_cfg->ctrl >= NPCM_PWDWN_CTL_COUNT) {
+		return -EINVAL;
+	}
+
+	/* Set related PD (Power-Down) bit of module to turn off clock */
+	NPCM_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit);
+	return 0;
+}
+
+static int npcm_clock_control_get_subsys_rate(const struct device *dev,
+					      clock_control_subsys_t sub_system,
+					      uint32_t *rate)
+{
+	ARG_UNUSED(dev);
+	struct npcm_clk_cfg *clk_cfg = (struct npcm_clk_cfg *)(sub_system);
+
+	switch (clk_cfg->bus) {
+	case NPCM_CLOCK_BUS_APB1:
+		*rate = NPCM_APB_CLOCK(1);
+		break;
+	case NPCM_CLOCK_BUS_APB2:
+		*rate = NPCM_APB_CLOCK(2);
+		break;
+	case NPCM_CLOCK_BUS_APB3:
+		*rate = NPCM_APB_CLOCK(3);
+		break;
+	case NPCM_CLOCK_BUS_AHB6:
+		*rate = CORE_CLK/(AHB6DIV_VAL + 1);
+		break;
+	case NPCM_CLOCK_BUS_FIU:
+		*rate = CORE_CLK/(FIUDIV_VAL + 1);
+		break;
+	case NPCM_CLOCK_BUS_CORE:
+		*rate = CORE_CLK;
+		break;
+	case NPCM_CLOCK_BUS_LFCLK:
+		*rate = LFCLK;
+		break;
+	case NPCM_CLOCK_BUS_FMCLK:
+		*rate = FMCLK;
+		break;
+	default:
+		*rate = 0U;
+		/* Invalid parameters */
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* Clock controller driver registration */
+static struct clock_control_driver_api npcm_clock_control_api = {
+	.on = npcm_clock_control_on,
+	.off = npcm_clock_control_off,
+	.get_rate = npcm_clock_control_get_subsys_rate,
+};
+
+static int npcm_clock_control_init(const struct device *dev)
+{
+	struct cdcg_reg *const inst_cdcg = HAL_CDCG_INST(dev);
+
+	/*
+	 * Resetting the OFMCLK (even to the same value) will make the clock
+	 * unstable for a little which can affect peripheral communication like
+	 * eSPI. Skip this if not needed.
+	 */
+	if (inst_cdcg->HFCGN != HFCGN_VAL || inst_cdcg->HFCGML != HFCGML_VAL
+			|| inst_cdcg->HFCGMH != HFCGMH_VAL) {
+		/*
+		 * Configure frequency multiplier M/N values according to
+		 * the requested OFMCLK (Unit:Hz).
+		 */
+		inst_cdcg->HFCGN  = HFCGN_VAL;
+		inst_cdcg->HFCGML = HFCGML_VAL;
+		inst_cdcg->HFCGMH = HFCGMH_VAL;
+
+		/* Load M and N values into the frequency multiplier */
+		inst_cdcg->HFCGCTRL |= BIT(NPCM_HFCGCTRL_LOAD);
+		/* Wait for stable */
+		while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCM_HFCGCTRL_CLK_CHNG))
+			;
+	}
+
+	/* Set all clock prescalers of core and peripherals. */
+	inst_cdcg->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL);
+	inst_cdcg->HFCBCD = (APB1DIV_VAL | (APB2DIV_VAL << 4));
+	inst_cdcg->HFCBCD1 = FIUDIV_VAL;
+	inst_cdcg->HFCBCD2 = APB3DIV_VAL;
+
+	return 0;
+}
+
+const struct npcm_pcc_config pcc_config = {
+	.base_cdcg = DT_INST_REG_ADDR_BY_NAME(0, cdcg),
+	.base_pmc  = DT_INST_REG_ADDR_BY_NAME(0, pmc),
+};
+
+DEVICE_DT_INST_DEFINE(0,
+		    &npcm_clock_control_init,
+		    NULL,
+		    NULL, &pcc_config,
+		    PRE_KERNEL_1,
+		    CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
+		    &npcm_clock_control_api);

drivers/gpio/CMakeLists.txt

@@ -52,6 +52,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX    gpio_nct38xx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX    gpio_nct38xx_port.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX_ALERT  gpio_nct38xx_alert.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NEORV32    gpio_neorv32.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_NPCM       gpio_npcm.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NPCX       gpio_npcx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NPM1300    gpio_npm1300.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NPM6001    gpio_npm6001.c)

drivers/gpio/Kconfig

@@ -138,6 +138,7 @@ source "drivers/gpio/Kconfig.mcux_rgpio"
 source "drivers/gpio/Kconfig.mmio32"
 source "drivers/gpio/Kconfig.nct38xx"
 source "drivers/gpio/Kconfig.neorv32"
+source "drivers/gpio/Kconfig.npcm"
 source "drivers/gpio/Kconfig.npcx"
 source "drivers/gpio/Kconfig.npm1300"
 source "drivers/gpio/Kconfig.npm6001"

drivers/gpio/Kconfig.npcm

@@ -0,0 +1,13 @@
+# NPCX GPIO driver configuration options
+
+# Copyright (c) 2024 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_NPCM
+	bool "Nuvoton NPCM enhance Super I/O (eSIO) gpio driver"
+	default y
+	depends on DT_HAS_NUVOTON_NPCM_GPIO_ENABLED
+	help
+	  This option enables the GPIO driver for NPCM family of
+	  processors.
+	  Say y if you wish to use serial port on NPCM MCU.