Sync code from npcm-v2.6

include/arch/arm/aarch32/mpu/arm_mpu_v7m.h

@@ -109,11 +109,17 @@
 #define REGION_2G       REGION_SIZE(2GB)
 #define REGION_4G       REGION_SIZE(4GB)
 
+
+/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
+ * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
+ * the SRAM region XN bit clear or the application code will not be executable.
+ */
+
 /* Some helper defines for common regions */
 #define REGION_RAM_ATTR(size) \
 { \
 	(NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \
-	 MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \
+	 IF_ENABLED(CONFIG_XIP, (MPU_RASR_XN_Msk |)) size | P_RW_U_NA_Msk) \
 }
 #define REGION_RAM_NOCACHE_ATTR(size) \
 { \

include/arch/arm/aarch32/mpu/arm_mpu_v8m.h

@@ -118,9 +118,16 @@
  * expected to be re-programmed or re-adjusted at run-time so
  * that they do not overlap with other MPU regions).
  */
+
+
+/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
+ * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
+ * the SRAM region XN bit clear or the application code will not be executable.
+ */
+
 #define REGION_RAM_ATTR(base, size) \
 	{\
-		.rbar = NOT_EXEC | \
+		.rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) \
 			P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
 		/* Cache-ability */ \
 		.mair_idx = MPU_MAIR_INDEX_SRAM, \

soc/arm/npcm4xx/common/CMakeLists.txt

@@ -12,7 +12,7 @@ zephyr_sources_ifdef(CONFIG_XIP
 )
 
 zephyr_linker_sources_ifdef(CONFIG_XIP
-  RAM_SECTIONS
+  SECTIONS
   SORT_KEY 0
   npcm4xx_sram_vector_table.ld
 )

soc/arm/npcm4xx/common/ImageGenerator/ImageGenerator.py

@@ -2016,7 +2016,8 @@ def RemoveOTP():
 # 0 NOTEST, 10 DEBUG, 20 INFO, 30 WARNING, 40 ERROR, 50 CRITICAL
 logging.basicConfig(level=20, format='%(asctime)s - %(levelname)s : %(message)s',
                     filemode='w', filename='Log.txt')
-os.system('color')
+if sys.platform == "win32":
+    os.system('color')
 argv = sys.argv
 logging.info('User input : %s' % argv)
 

soc/arm/npcm4xx/common/npcm4xx_sram_vector_table.ld

@@ -3,8 +3,9 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-SECTION_PROLOGUE(.npcm4xx_sram_vector_table,,)
+SECTION_DATA_PROLOGUE(.npcm4xx_sram_vector_table,,)
 {
+_npcm4xx_sram_vector_begin = .;
 #if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)
 /*
  * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the
@@ -29,6 +30,7 @@ SECTION_PROLOGUE(.npcm4xx_sram_vector_table,,)
 . = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
 #endif
 
+MPU_ALIGN(_npcm4xx_sram_vector_table_size);
 /* vector table from initial SP(0x00) to systick(0x3C) */
 _npcm4xx_sram_vector_start = .;
 KEEP(*(.npcm4xx_exc_sram_vector_table))
@@ -44,6 +46,7 @@ _npcm4xx_sram_irq_vector_end = .;
 _npcm4xx_sram_vector_func_start = .;
 KEEP(*(.npcm4xx_sram_vector_func))
 KEEP(*(".npcm4xx_sram_vector_func.*"))
+MPU_ALIGN(_npcm4xx_sram_vector_table_size);
 _npcm4xx_sram_vector_func_end = .;
 
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
@@ -54,4 +57,4 @@ _npcm4xx_sram_vector_func_end = .;
 _npcm4xx_sram_vector_table_size = _npcm4xx_sram_vector_func_end - _npcm4xx_sram_vector_start;
 
 /* use for load code from rom to sram */
-_npcm4xx_rom_vector_table_start = LOADADDR(.npcm4xx_sram_vector_table);
+_npcm4xx_rom_vector_table_start = LOADADDR(.npcm4xx_sram_vector_table) + (_npcm4xx_sram_vector_start - _npcm4xx_sram_vector_begin);

soc/arm/npcm4xx/npcm400f/CMakeLists.txt

@@ -1,8 +1,14 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m)
 
 zephyr_sources(
   soc.c
   gdma.c
 )
+
+zephyr_sources_ifdef(
+  CONFIG_ARM_MPU
+  mpu_regions.c
+)

soc/arm/npcm4xx/npcm400f/Kconfig.series

@@ -10,5 +10,7 @@ config SOC_SERIES_NPCM400F
 	select CPU_CORTEX_M_HAS_DWT
 	select SOC_FAMILY_NPCM4XX
 	select CORTEX_M_SYSTICK
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	help
 	  Enable support for Nuvoton NPCM400F series

soc/arm/npcm4xx/npcm400f/mpu_regions.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/slist.h>
+#include <arch/arm/aarch32/mpu/arm_mpu.h>
+
+#include "arm_mpu_mem_cfg.h"
+
+extern char _npcm4xx_sram_vector_start[];
+
+/* Some helper defines for nuvton regions, the same attr with ramfunc */
+#define NUVOTON_REGION_RAM_RX_ATTR(size)                                           \
+	{                                                                          \
+		(NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \
+		 size | P_RO_U_RO_Msk)                                             \
+	}
+
+static const struct arm_mpu_region mpu_regions[] = {
+	/* Region 0 */
+	MPU_REGION_ENTRY("FLASH_0",
+			 CONFIG_FLASH_BASE_ADDRESS,
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+			 REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \
+				 CONFIG_FLASH_SIZE * 1024)),
+#else
+			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
+#endif
+	/* Region 1 */
+	MPU_REGION_ENTRY("SRAM_0",
+			 CONFIG_SRAM_BASE_ADDRESS,
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+			 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \
+				 CONFIG_SRAM_SIZE * 1024)),
+#else
+			 REGION_RAM_ATTR(REGION_SRAM_SIZE)),
+#endif
+	/* Region 2 ,use for sram vector table, size 512 bytes */
+#if defined(CONFIG_XIP)
+	MPU_REGION_ENTRY("SRAM_VECTOR_0",
+			(uint32_t)_npcm4xx_sram_vector_start,
+			NUVOTON_REGION_RAM_RX_ATTR(REGION_512B)),
+#endif
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

soc/arm/npcm4xx/npcm400f/soc.c

@@ -12,27 +12,24 @@
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
-uintptr_t scfg_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(scfg), 0);
-
 void z_platform_init(void)
 {
+	uintptr_t scfg_base = SCFG_BASE_ADDR;
 	struct scfg_reg *inst_scfg = (struct scfg_reg *)scfg_base;
 
-	if (scfg_base) {
-#if CONFIG_GPIO_NPCM4XX_RESET_SL_POWER_UP
-		inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_POWER;
+#ifdef CONFIG_GPIO_NPCM4XX_RESET_SL_POWER_UP
+	inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_POWER;
 #else
-		inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_CORE;
+	inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_CORE;
 #endif
-	}
+
+	npcm4xx_sram_vector_table_copy();
 }
 
 static int soc_init(const struct device *dev)
 {
 	ARG_UNUSED(dev);
 
-	npcm4xx_sram_vector_table_copy();
-
 	return 0;
 }