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fix(DM): standalonedm support apb #4172

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fix(DM): standalonedm support apb #4172

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032466f
fix(DM): standalonedm support apb
wissygh Jan 14, 2025
b5de476
submodule(rocket-chip): bump rocket-chip to support apb
wissygh Jan 14, 2025
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2 changes: 1 addition & 1 deletion rocket-chip
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Submodule rocket-chip updated 1 files
+3 −3 src/main/scala/devices/debug/Debug.scala
24 changes: 24 additions & 0 deletions src/main/scala/device/RocketDebugWrapper.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,10 @@ class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
// debug.node := TLFragmenter() := peripheralXbar
val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
debug.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
(apbDebugNodeOpt zip debug.apbNodeOpt) foreach { case (master, slave) =>
slave := master
}

// debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
// l2xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
Expand Down Expand Up @@ -74,6 +78,26 @@ class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
io.debugIO.extTrigger.foreach { x => debug.module.io.extTrigger.foreach {y => x <> y}}
debug.module.io.ctrl.debugUnavail.foreach { _ := false.B }

io.debugIO.apb.zip(apbDebugNodeOpt).map{case(io, apbNodeOpt) =>
val apb = apbNodeOpt.out(0)._1
apb.psel := io.psel
apb.penable := io.penable

apb.pwrite := io.pwrite
apb.paddr := io.paddr
apb.pprot := io.pprot
apb.pwdata := io.pwdata
apb.pstrb := io.pstrb
apb.pauser := io.pauser

io.pready := apb.pready
io.pslverr := apb.pslverr
io.prdata := apb.prdata
io.pduser := apb.pduser
}
debug.module.io.apb_clock.foreach(_ := io.debugIO.apb.get.clock)
debug.module.io.apb_reset.foreach(_ := io.debugIO.apb.get.reset)

val dtm = io.debugIO.systemjtag.map(instantiateJtagDTM(_))

def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
Expand Down
7 changes: 6 additions & 1 deletion src/main/scala/device/standalone/StandAloneDevice.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ import chisel3.experimental.{annotate, ChiselAnnotation}
import chisel3.experimental.dataview._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.tilelink._
Expand Down Expand Up @@ -169,6 +169,7 @@ object ArgParser {
var firrtlOpts = Array[String]()
var module: String = ""
var useTL: Boolean = false
var useAPB: Boolean = false
var baseAddress: BigInt = -1
var addrWidth: Int = -1
var dataWidth: Int = 64
Expand All @@ -185,6 +186,9 @@ object ArgParser {
case "--use-axi4" :: tail =>
useTL = false
nextOption(tail)
case "--use-apb" :: tail =>
useAPB = true
nextOption(tail)
case "--device-base-addr" :: value :: tail =>
baseAddress = value match {
case s"0x$hex" => BigInt(hex, 16)
Expand Down Expand Up @@ -222,6 +226,7 @@ object ArgParser {
useTL, baseAddress, addrWidth, dataWidth, p(XSTileKey).size
)(p)))(p.alter((site, here, up) => {
case DebugModuleKey => up(DebugModuleKey).map(_.copy(baseAddress = baseAddress))
case ExportDebug => up(ExportDebug).copy(protocols = (if(useAPB) Set(APB) else Set(JTAG)))
}))
case _: String => throw new IllegalArgumentException(s"$module not found")
}
Expand Down
4 changes: 4 additions & 0 deletions src/main/scala/device/standalone/standalone_device.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,10 @@ ifeq ($(DEVICE_AXI4),1)
DEVICE_ARGS += --use-axi4
endif

ifeq ($(DEVICE_APB),1)
DEVICE_ARGS += --use-apb
endif

ifneq ($(DEVICE_HART_NUM),)
NUM_CORES = $(DEVICE_HART_NUM)
endif
Expand Down
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