palladium.mk: rename RELEASE_WITH_ASSERT to SYNTHESIS #263
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We will generate same verilog code for both SYNTHESIS/no-SYNTHESIS version. It should be more simple and clear.
poemonsense
approved these changes
Jan 22, 2024
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We will generate same verilog code for both SYNTHESIS/no-SYNTHESIS version.
It should be more simple and clear.
Command may be as follows:
In XiangShan/Nutshell/Other Design：
Build:
make sim-verilog PLDM=1 WITH_CHISELDB=0 WITH_CONSTANTIN=0 MFC=1
make pldm-build SYNTHESIS=1 (no-diff) || make pldm-build (with-diff)
To add extra Macros, we can pass PLDM_EXTRA_MACRO="+define+xxx +define+yyy"
Run:
make pldm-run/pldm-debug SYNTHESIS=1 (no-diff) || make pldm-run/pldm-debug (with-diff)
To add extra running args, we can pass PLDM_EXTRA_ARGS="+workload=../../ready-to-run/microbench.bin +diff=../../ready-to-run/riscv64-nemu-interpreter-so". Note that relative paths should be based on build/pldm-compile