RISC-V

Simple and non optimized implementation of a RISC-V processor. This RISC-V pipeline is based on the DLX architecture.

Implementation: RISC-V32I

Current state:

Name		Name	Last commit message	Last commit date
Latest commit History 84 Commits
ConvBINHEX		ConvBINHEX
OP_GEN		OP_GEN
RISCV.hw		RISCV.hw
RISCV.ip_user_files		RISCV.ip_user_files
RISCV.sim/sim_1/behav/xsim		RISCV.sim/sim_1/behav/xsim
RISCV.srcs		RISCV.srcs
SIM_DATA		SIM_DATA
.gitignore		.gitignore
README.md		README.md
RISCV.png		RISCV.png
RISCV.xpr		RISCV.xpr