EDA-info

the awesome work, project and lab of EDA. continue update...

• Main EDA lab and open-source project：

  • Bei Yu, The Chinese University of Hong Kong
  • Evangeline F.Y. Young, The Chinese University of Hong Kong
  • Yibo Lin, The Peking Unbiversity
  • The UT Design Automation Laboratory (UTDA)
  • iEDA

• Placement and Routing

  • Routing:
    • FastRoute : A Step to Integrate Global Routing into Placement
    • NTHU : A New Global Router for Modern Designs
    • SAGERoute : Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility
    • Dr.CU : Dr. CU is a VLSI detailed routing tool
    • Dr.GR : Dr. CU is a VLSI global routing tool
    • Align : analog detailed router
    • Electromigration- and Parasitic-Aware ILP-Based Analog Router : analog global router
    • Efficient ILP-Based Variant-Grid Analog Router : analog global router
  • placement:
    • Xplace : An Extremely Fast and Extensible Global Placement Framework
    • RePlace : Advancing Solution Quality and Routability Validation in Global Placement
    • DreamPlace : Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
    • ePlace : Electrostatics based Placement using Fast Fourier Transform and Nesterov’s Method
    • MacroPlacement : Assessment of Reinforcement Learning for Macro Placement
    • MaskPlace : Fast Chip Placement via Reinforced Visual Representation Learning
  • analog layout generation
    • Laygo : A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies
    • BAG : A Process-Portable Framework for Generator-based AMS Circuit Design
    • MAGICAL : Machine Generated Analog IC Layout
    • ALIGN : Analog Layout, Intelligently Generated from Netlists
    • Symmetry Annotation Extraction : Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks

• Analog Circuit Design Optimization

  • Multi-objective Bayesian Optimization for Analog/RF Circuit Synthesis
  • Automated Design of Analog Circuits Using Reinforcement Learning
    • code
  • DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks
  • MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors
  • DC-Model: A New Method for Assisting the Analog Circuit Optimization
  • An efficient batch-constrained bayesian optimization approach for analog circuit synthesis via multiobjective acquisition ensemble
  • Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design
    • code
  • Geometric programming for circuit optimization
  • A tutorial on geometric programming
  • Late Breaking Results: Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization
  • Learning to Design Circuits
  • GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
  • Closing the Design Loop: Bayesian Optimization AssistedHierarchical Analog Layout Synthesis

• Layout Pattern Generation

  • DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder
  • Layout Pattern Generation and Legalization with Generative Learning Models
  • LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling
  • DiffPattern : Layout Pattern Generation via Discrete Diffusion