Full-custom-design-of-comparator

In the present real time world, due to the improvements and innovations of integrated System on Chip (SoC) applications there is a requirement to integrate of technology, Electronic Device design is an integration of analog, digital, mixed signal design. As, comparator is one of the basic circuitries used in arithmetic unit of various portable devices.

The Demand and popularity of any device depends on the non-functional parameter such as area, speed, battery life and reliability. The main issues in performance estimation are Area Consumption, Power dissipation, Propagation delay and Power Delay Product. These performance criteria’s should be individually investigated, analyzed for the various designs of the comparator by different logic styles.

The comparator design can be realized by using various design topologies. Some of the vividly used techniques are Conventional CMOS logic, Pass Transistor Logic (PTL), Gate Diffusion Input (GDI) Logic, Stacking technique, Quantum-dot cellular automata etc. The selection of the design topology comparator is done based on the non-functional parameters of the design and its constraints. The performance functional parameters are improved by combining the topology architectures of different design techniques.

In this work, the comparator is designed by using conventional CMOS logic, PTL, GDI, and Mixed Logic topology by using 45nm technology. These circuits are designed by using Cadence Virtuoso EDA design tools. The simulation results and non�functional performance parameters are analyzed for different topology environments.

Keywords: VLSI Design, Comparator, Datapath, EDA tools ,CMOS Logic, GDI Logic, PTL Logic.