create new folder for uop arch

source_code/pipelines/stage4/include/stage3_fetch_execute_if.vh

@@ -0,0 +1,60 @@
+/*
+*   Copyright 2016 Purdue University
+*   
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*   
+*       http://www.apache.org/licenses/LICENSE-2.0
+*   
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*   
+*   
+*   Filename:     stage3_fetch_execute_if.vh
+*   
+*   Created by:   Jacob R. Stevens	
+*   Email:        [email protected]
+*   Date Created: 06/01/2016
+*   Description:  Interface between the fetch and execute pipeline stages
+*/
+
+`ifndef STAGE3_FETCH_EXECUTE_IF_VH
+`define STAGE3_FETCH_EXECUTE_IF_VH
+
+interface stage3_fetch_execute_if;
+  import rv32i_types_pkg::*;
+  import stage3_types_pkg::*;
+
+  fetch_ex_t fetch_ex_reg;
+  word_t brj_addr;
+
+  uop_t[0:0] s_ctrls; 
+  logic[3:0] s_num_uops;
+
+  uop_t uop;  
+
+  modport fetch(
+    output fetch_ex_reg
+  );
+
+  modport execute(
+    input uop
+    //input fetch_ex_reg
+  );
+
+  modport s_decode(
+    input fetch_ex_reg, 
+    output s_ctrls, s_num_uops
+  ); 
+
+  modport queue(
+    input s_ctrls, s_num_uops, 
+    output uop
+  ); 
+
+endinterface
+`endif

source_code/pipelines/stage4/include/stage3_forwarding_unit_if.vh

@@ -0,0 +1,32 @@
+`ifndef __STAGE3_FORWARD_UNIT_VH__
+`define __STAGE3_FORWARD_UNIT_VH__
+
+interface stage3_forwarding_unit_if();
+
+    rv32i_types_pkg::regsel_t rd_m;
+    rv32i_types_pkg::regsel_t rs1_e;
+    rv32i_types_pkg::regsel_t rs2_e;
+    logic reg_write;
+    logic load;
+    logic fwd_rs1;
+    logic fwd_rs2;
+    rv32i_types_pkg::word_t rd_mem_data;
+
+    modport execute(
+        input fwd_rs1, fwd_rs2, rd_mem_data,
+        output rs1_e, rs2_e
+    );
+
+    modport mem(
+        output rd_m, rd_mem_data, reg_write, load
+    );
+
+    modport fw_unit(
+        input rs1_e, rs2_e, rd_m, reg_write, load,
+        output fwd_rs1, fwd_rs2
+    );
+
+endinterface
+
+
+`endif

source_code/pipelines/stage4/include/stage3_hazard_unit_if.vh

@@ -0,0 +1,126 @@
+/*
+*   Copyright 2016 Purdue University
+*
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*
+*       http://www.apache.org/licenses/LICENSE-2.0
+*
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*
+*
+*   Filename:     stage3_hazard_unit_if.vh
+*
+*   Created by:   Jacob R. Stevens
+*   Email:        [email protected]
+*   Date Created: 06/15/2016
+*   Description:  Interface for the hazard unit of the two stage pipeline
+*/
+
+`ifndef STAGE3_HAZARD_UNIT_IF_VH
+`define STAGE3_HAZARD_UNIT_IF_VH
+
+interface stage3_hazard_unit_if();
+
+  import rv32i_types_pkg::word_t;
+  import rv32i_types_pkg::regsel_t;
+
+  // Pipeline status signals (inputs)
+  regsel_t rs1_e, rs2_e;
+  regsel_t rd_m;
+  logic reg_write, csr_read;
+  logic i_mem_busy, d_mem_busy, dren, dwen, ret, suppress_data;
+  logic jump, branch, fence_stall;
+  logic mispredict, halt;
+  word_t pc_f, pc_e, pc_m;
+  logic valid_e, valid_m; // f always valid since it's the PC
+  logic ifence;
+  logic ex_busy;
+  logic lsc_queue_full;
+
+  // Control (outputs)
+  logic pc_en, npc_sel;
+  logic if_ex_flush, ex_mem_flush;
+  logic if_ex_stall, ex_mem_stall;
+  logic iren, suppress_iren;
+  logic rollback; // signal for rolling back fetched instructions after instruction in mem stage, for certain CSR and ifence instructions
+
+  // xTVEC Insertion
+  word_t priv_pc;
+  logic insert_priv_pc;
+
+  //Pipeline Exceptions (inputs)
+  logic fault_insn, mal_insn, illegal_insn, fault_l, mal_l, fault_s, mal_s,
+        breakpoint, env, wfi;
+  word_t badaddr;
+
+  // Pipeline Tokens
+  logic token_ex;
+  logic token_mem;
+
+  // RV32C
+  logic rv32c_ready;
+
+
+  // uop stage 
+  logic stall_queue, flush_queue, is_queue_full;
+  logic valid_decode; 
+  word_t
+  pc_decode; 
+
+
+  modport hazard_unit (
+    input   rs1_e, rs2_e, rd_m,
+            reg_write, csr_read,
+            i_mem_busy, d_mem_busy, dren, dwen, ret,
+            jump, branch, fence_stall, mispredict, halt, pc_f, pc_e, pc_m,
+            fault_insn, mal_insn, illegal_insn, fault_l, mal_l, fault_s, mal_s, breakpoint, env, wfi,
+            badaddr, ifence,
+            token_ex, token_mem, rv32c_ready,
+            valid_e, valid_m, ex_busy,
+
+            is_queue_full, pc_decode, valid_decode,
+
+
+    output  pc_en, npc_sel,
+            if_ex_flush, ex_mem_flush,
+            if_ex_stall, ex_mem_stall,
+            priv_pc, insert_priv_pc, iren, suppress_iren, suppress_data, rollback, 
+
+            stall_queue, flush_queue
+
+  );
+
+  modport fetch (
+    input   pc_en, npc_sel, if_ex_stall, if_ex_flush, priv_pc, insert_priv_pc, iren, suppress_iren, rollback,
+    output  i_mem_busy, rv32c_ready, pc_f
+  );
+
+  modport queue (
+    input stall_queue, flush_queue, 
+    output is_queue_full, pc_decode, valid_decode
+  ); 
+
+  modport execute (
+    input  ex_mem_stall, ex_mem_flush, npc_sel,
+    output rs1_e, rs2_e, token_ex, pc_e, valid_e, ex_busy
+  );
+
+  modport mem (
+    input   ex_mem_stall, ex_mem_flush, suppress_data,
+    output  rd_m, reg_write, csr_read,
+            d_mem_busy, dren, dwen, ret,
+            jump, branch, fence_stall, mispredict, halt, pc_m, valid_m,
+            fault_insn, mal_insn, illegal_insn, fault_l, mal_l, fault_s, mal_s, breakpoint, env,
+            badaddr, ifence, wfi,
+            token_mem
+  );
+
+ endinterface
+
+`endif

source_code/pipelines/stage4/include/stage3_mem_pipe_if.vh

@@ -0,0 +1,34 @@
+`ifndef __STAGE3_MEM_PIPE_IF__
+`define __STAGE3_MEM_PIPE_IF__
+
+interface stage3_mem_pipe_if();
+
+    import rv32i_types_pkg::*;
+    import stage3_types_pkg::*;
+
+    logic reg_write;
+    regsel_t rd_m;
+    ex_mem_t ex_mem_reg;
+    word_t brj_addr;
+    word_t reg_wdata;
+    word_t pc4; // For flush in case of fence_i, CSR, etc.
+
+    modport fetch(
+        input brj_addr, pc4
+    );
+
+
+    modport execute(
+        input reg_wdata, reg_write, rd_m,
+        output ex_mem_reg
+    );
+
+    modport mem(
+        input ex_mem_reg,
+        output brj_addr, reg_wdata, reg_write, rd_m, pc4
+    );
+
+endinterface
+
+
+`endif

source_code/pipelines/stage4/include/uop_if.vh

@@ -0,0 +1,38 @@
+`ifndef STAGE3_UOP_IF_VH
+`define STAGE3_UOP_IF_VH
+
+interface uop_if;
+  import rv32i_types_pkg::*;
+  import stage3_types_pkg::*;
+
+  fetch_ex_t fetch_ex_reg;
+  word_t brj_addr;
+
+  modport ctrls_in(
+    output fetch_ex_reg
+  );
+
+  modport ctrls_out(
+    output fetch_ex_reg
+  ); 
+
+  modport rf_out(
+    output fetch_ex_reg
+  );
+
+  modport fetch_in(
+
+  );
+
+  modport fetch_out(
+
+  ); 
+
+
+  modport execute(
+    input fetch_ex_reg
+  );
+
+endinterface
+
+`endif