Vector Extension

[1fahadaloufi]

Implement zve32x subset of the RISC-V vector extension without fixed point instructions. Documentation about this vector extension implementation is in doc/src/rv32v.

[maxmichalec]

TODO before merge:

• Replace *_wide signals in vector mem stage / coalescer
• Add atomics support to vector load-store controller

[devins2518]

Looks good so far. Once the coalescer is fixed and there's a bit of cleanup, I think its ready to merge

[devins2518]

This is more of a general comment on the rv32v asm files, a majority of the benchmarking files is usually the test data from what I've seen, is it reused enough that the common data can be pulled out into a helper file that each benchmark file includes?

[devins2518]

What's the purpose of these hidden files?

[devins2518]

Is it possible to use the stage3 fetch so that any fixes can be shared by both

[devins2518]

Same with the hazard unit, could we pull it out to be "pipeline agnostic" and enable certain parts depending on the pipeline config

[devins2518]

Also are there any defines for the tests that I can change to have more test coverage?

[maxmichalec]

Tests are passing with *_wide signals removed. Also fixed passthrough reads bug (@devins2518 check that the fix is OK). For cacheable blocks, the whole block can be written to if the address is block-aligned, otherwise only one block is written to/read from at a time. Non-cacheable, potentially non-idempotent, regions only deal with word-wide accesses (the vector memory controller is aware of this and every access is serialized and in-order). This wouldn't be too difficult to widen in the future once the AHB bus is widened.

Will cleanup next and we should add tests for 2 cores running vector code.

[devins2518]

Looks good so far, nice catch on the pass through bug. The write strategy makes sense and seems to be pretty simple implementation wise.

[devins2518]

Nice catch, this looks good. The conditional probably isn't needed but it should be fine