Merge pull request #7 from PyFPGA/0.1.1

0.1.1

README.md

@@ -3,6 +3,8 @@
 HDL converter (between VHDL, SystemVerilog and/or Verilog), based on [GHDL](https://github.com/ghdl/ghdl), [Yosys](https://github.com/YosysHQ/yosys), [Synlig](https://github.com/chipsalliance/synlig) and the plugins [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) and [yosys-slang](https://github.com/povik/yosys-slang).
 It relies on [Docker](https://docs.docker.com/get-docker) and [PyFPGA containers](https://github.com/PyFPGA/containers).
 
+> Known limitation: the files must be located either under the `$HOME` directory or under the current working directory (`$PWD`) for Docker to be able to find and access them.
+
 * `vhdl2vhdl`: converts from a newer VHDL to VHDL'93 (using `ghdl`).
 * `vhdl2vlog`: converts from VHDL to Verilog (backends: `ghdl` or `yosys`).
 * `slog2vlog`: converts from SystemVerilog to Verilog (frontends: `slang`, `synlig` or `yosys`).
@@ -11,7 +13,7 @@ It relies on [Docker](https://docs.docker.com/get-docker) and [PyFPGA containers
 
 ```
 usage: vhdl2vhdl [-h] [-v] [-g GENERIC VALUE] [-a ARCH] [-f FILENAME]
-                 [-o PATH] [-t TOPNAME]
+                 [-o PATH] -t TOPNAME
                  FILE[,LIBRARY] [FILE[,LIBRARY] ...]
 
 VHDL to VHDL
@@ -27,15 +29,15 @@ optional arguments:
                         times)
   -a ARCH, --arch ARCH  specify a top-level Architecture
   -f FILENAME, --filename FILENAME
-                        resulting file name [<TOPNAME>.vhdl]
+                        resulting file name [<TOPNAME>.<EXT>]
   -o PATH, --odir PATH  output directory [results]
   -t TOPNAME, --top TOPNAME
                         specify the top-level of the design
 ```
 
 ```
 usage: vhdl2vlog [-h] [-v] [--backend TOOL] [-g GENERIC VALUE] [-a ARCH]
-                 [-f FILENAME] [-o PATH] [-t TOPNAME]
+                 [-f FILENAME] [-o PATH] -t TOPNAME
                  FILE[,LIBRARY] [FILE[,LIBRARY] ...]
 
 VHDL to Verilog
@@ -52,16 +54,16 @@ optional arguments:
                         times)
   -a ARCH, --arch ARCH  specify a top-level Architecture
   -f FILENAME, --filename FILENAME
-                        resulting file name [<TOPNAME>.v]
+                        resulting file name [<TOPNAME>.<EXT>]
   -o PATH, --odir PATH  output directory [results]
   -t TOPNAME, --top TOPNAME
                         specify the top-level of the design
 ```
 
 ```
 usage: slog2vlog [-h] [-v] [--frontend TOOL] [-p PARAM VALUE]
-                 [-d DEFINE VALUE] [-i PATH] [-f FILENAME] [-o PATH]
-                 [-t TOPNAME]
+                 [-d DEFINE VALUE] [-i PATH] [-f FILENAME] [-o PATH] -t
+                 TOPNAME
                  FILE [FILE ...]
 
 SystemVerilog to Verilog
@@ -82,7 +84,7 @@ optional arguments:
                         specify an Include Path (can be specified multiple
                         times)
   -f FILENAME, --filename FILENAME
-                        resulting file name [<TOPNAME>.v]
+                        resulting file name [<TOPNAME>.<EXT>]
   -o PATH, --odir PATH  output directory [results]
   -t TOPNAME, --top TOPNAME
                         specify the top-level of the design

hdlconv/__init__.py

@@ -1,3 +1,3 @@
 """hdlconv version"""
 
-__version__ = '0.1.0'
+__version__ = '0.1.1'

hdlconv/core.py

@@ -50,7 +50,6 @@ def get_args(src, dst):
     else:
         metavar = 'FILE'
         helpmsg = 'System Verilog file/s'
-    filename = '<TOPNAME>.vhdl' if dst == 'vhdl' else '<TOPNAME>.v'
     parser.add_argument(
         '-v', '--version',
         action='version',
@@ -109,8 +108,7 @@ def get_args(src, dst):
     parser.add_argument(
         '-f', '--filename',
         metavar='FILENAME',
-        default=filename,
-        help=f'resulting file name [{filename}]'
+        help='resulting file name [<TOPNAME>.<EXT>]'
     )
     parser.add_argument(
         '-o', '--odir',
@@ -121,7 +119,8 @@ def get_args(src, dst):
     parser.add_argument(
         '-t', '--top',
         metavar='TOPNAME',
-        help='specify the top-level of the design'
+        help='specify the top-level of the design',
+        required=True
     )
     parser.add_argument(
         'files',
@@ -231,6 +230,9 @@ def hdlconv(src, dst):
     """HDL conversion entry-point"""
     check_docker()
     args = get_args(src, dst)
+    if args.filename is None:
+        args.filename = args.top.lower()
+        args.filename += '.vhdl' if dst == 'vhdl' else '.v'
     data = get_data(src, dst, args)
     template = get_template(src, dst, args)
     content = get_content(template, data)

hdlconv/templates/docker.jinja

@@ -1,2 +1,2 @@
 CONTAINER="ghcr.io/pyfpga/synthesis"
-DOCKER="docker run --rm -v $HOME:$HOME -w $PWD --user $(id -u):$(id -g) $CONTAINER"
+DOCKER="docker run --rm -v $HOME:$HOME -v $PWD:$PWD -w $PWD --user $(id -u):$(id -g) $CONTAINER"

tests/run.sh

@@ -4,6 +4,12 @@ set -e
 
 export PYTHONPATH=$(pwd)/..
 
+python3 ../hdlconv/vhdl2vhdl.py --top Counter hdl/vhdl/counter.vhdl
+
+python3 ../hdlconv/vhdl2vlog.py --top Counter hdl/vhdl/counter.vhdl
+
+python3 ../hdlconv/slog2vlog.py --top Counter hdl/slog/counter.sv
+
 python3 ../hdlconv/vhdl2vhdl.py --filename conv1.vhdl \
   --top Counter hdl/vhdl/counter.vhdl