About control flow analysis

[earphonebreaker]

I tried the control flow analysis in ./example/ and I was wondering that what is the requirements of extracting an FSM for a verilog design? i.e. when I try to extract FSM from the following RTL (which is a simple DFF with asyn-reset), the result is None.

module test(
    input clk,
    input rst_n,
    input w,
    output y,
);
 
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        y <= 0;
    end
    else begin
        y <= w;
    end
end
endmodule

So I suppose there must be a loop in the given FSM, such that the control flow analyzer could recognize it. Is it correct? Further more, if the analysis result is None, it means there should be no loops in the circuits. Is it correct?