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71 Open 24 Closed
71 Open 24 Closed
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Issues list

Bug: ports mentioned in verilog file are taken as declaration.
#135 opened Jan 30, 2025 by rahultanwar10
Request: Add generated API documentation for this library
#134 opened Nov 28, 2024 by parker-research
Feature Request: Add strong typing to this library
#133 opened Nov 28, 2024 by parker-research
TypeError: generate() got an unexpected keyword argument 'reorder' line 100 in Pyverilog/examples/example_graphgen.py
#131 opened Jul 13, 2024 by zhangshuaiAA9
2
ANSI Style localparam causes parsing error
#129 opened Jun 15, 2024 by mclark-iontra
Codegen arrays
#128 opened Oct 30, 2023 by CapucinedeBoissac
Unsized numbers without base solution
#127 opened Oct 30, 2023 by YSJL
parser error
#126 opened Oct 20, 2023 by 1353369570
Attribute error in parser
#125 opened Oct 15, 2023 by KatCe
Parse Error: Cannot parse a function
#124 opened Oct 15, 2023 by KatCe
1
AST node
#122 opened Oct 5, 2023 by lijiale6224
1
Can not support "generate case" statement
#121 opened Jun 3, 2023 by TonyLiaoZP
unsufficient parse for large scale verilog design
#118 opened Mar 14, 2023 by ZhaoYunfei123
TypeError: generate() got an unexpected keyword argument 'reorder'
#117 opened Feb 22, 2023 by Sanjaya97
3
Unsized numbers without base not supported
#116 opened Feb 19, 2023 by Louis-DR
2
Specify statements
#115 opened Feb 2, 2023 by lilasrahis
Parsing Issues
#114 opened Oct 27, 2022 by kwmartin
1
ParseError for User Defined Primitives wontfix
#113 opened Oct 25, 2022 by TheMatt2
1
Parser Error for resettable D Flip-Flop
#112 opened Oct 11, 2022 by kwmartin
1
Parse Error for Inverter Gate
#111 opened Oct 11, 2022 by kwmartin
Parsing Error for integer memories
#110 opened Sep 19, 2022 by kwmartin
dataflow analysis error
#109 opened Aug 8, 2022 by cemery123
5
Extracting design information via API
#108 opened Aug 4, 2022 by svenka3
About control flow analysis
#105 opened May 25, 2022 by earphonebreaker
A bug when parsing nesting ifStatement
#102 opened Apr 10, 2022 by Yang-Qirui
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