Merge pull request #2 from QuickLogic-Corp/qf_helloworldhw

added new led driver for S3. Added qf_helloworldhw sample. The led dr…

drivers/led/CMakeLists.txt

@@ -4,5 +4,6 @@ zephyr_sources_ifdef(CONFIG_HT16K33 ht16k33.c)
 zephyr_sources_ifdef(CONFIG_LP3943 lp3943.c)
 zephyr_sources_ifdef(CONFIG_LP5562 lp5562.c)
 zephyr_sources_ifdef(CONFIG_PCA9633 pca9633.c)
+zephyr_sources_ifdef(CONFIG_EOS_S3_LED1 led_eos_s3_1.c)
 
 zephyr_sources_ifdef(CONFIG_USERSPACE   led_handlers.c)

drivers/led/Kconfig

@@ -24,5 +24,6 @@ source "drivers/led/Kconfig.ht16k33"
 source "drivers/led/Kconfig.lp3943"
 source "drivers/led/Kconfig.lp5562"
 source "drivers/led/Kconfig.pca9633"
+source "drivers/led/Kconfig.eos_s3_1"
 
 endif # LED

drivers/led/Kconfig.eos_s3_1

@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Workaround GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config EOS_S3_LED1
+	bool "EOS S3 LED driver 1"
+	help
+	  Enable LED driver 1 for QL S3.
+

drivers/led/eos_s3_led_config.h

@@ -0,0 +1,58 @@
+/*
+ * ==========================================================
+ *
+ *    Copyright (C) 2020 QuickLogic Corporation             
+ *    Licensed under the Apache License, Version 2.0 (the "License");
+ *    you may not use this file except in compliance with the License.
+ *    You may obtain a copy of the License at
+ * 		http://www.apache.org/licenses/LICENSE-2.0
+ *    Unless required by applicable law or agreed to in writing, software
+ *    distributed under the License is distributed on an "AS IS" BASIS,
+ *    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *    See the License for the specific language governing permissions and
+ *    limitations under the License.
+ *
+ *    File      : eos_s3_led_config.h
+ *    Purpose   : This file contains the IO mux definitions for LEDs
+ *    		                                                            
+ *                                                          
+ * ===========================================================
+ *
+ */
+
+
+#ifndef _INC_EOS_S3_LED_CONFIG
+#define _INC_EOS_S3_LED_CONFIG
+
+#include <soc_pinmap.h>
+
+/* Set FPGA_LED0 to PAD18 */
+#define FPGA_LED0_PAD18 (PAD_CTRL_SEL_FPGA | PAD_OEN_NORMAL \
+	| PAD_P_Z | PAD_SR_SLOW | PAD_E_4MA \
+	| PAD_REN_DISABLE | PAD_SMT_DISABLE)
+#define FPGA_LED0_PAD18_FBIO PAD18_FUNC_SEL_FBIO_18
+
+/* Set FPGA_LED1 to PAD21 */
+#define FPGA_LED1_PAD21 (PAD_CTRL_SEL_FPGA | PAD_OEN_NORMAL \
+	| PAD_P_Z | PAD_SR_SLOW | PAD_E_4MA \
+	| PAD_REN_DISABLE | PAD_SMT_DISABLE)
+#define FPGA_LED1_PAD21_FBIO PAD21_FUNC_SEL_FBIO_21
+
+/* Set FPGA_LED2 to PAD22 */
+#define FPGA_LED2_PAD22 (PAD_CTRL_SEL_FPGA | PAD_OEN_NORMAL \
+	| PAD_P_Z | PAD_SR_SLOW | PAD_E_4MA \
+	| PAD_REN_DISABLE | PAD_SMT_DISABLE)
+#define FPGA_LED2_PAD22_FBIO PAD22_FUNC_SEL_FBIO_22
+
+#define FPGA_LED0_PAD		18
+#define FPGA_LED0_PAD_CFG	FPGA_LED0_PAD18
+#define FPGA_LED0_FBIO_SEL	FPGA_LED0_PAD18_FBIO
+#define FPGA_LED1_PAD		21
+#define FPGA_LED1_PAD_CFG	FPGA_LED1_PAD21
+#define FPGA_LED1_FBIO_SEL	FPGA_LED1_PAD21_FBIO
+#define FPGA_LED2_PAD		22
+#define FPGA_LED2_PAD_CFG	FPGA_LED2_PAD22
+#define FPGA_LED2_FBIO_SEL	FPGA_LED2_PAD22_FBIO
+
+
+#endif /* _INC_EOS_S3_LED_CONFIG */

drivers/led/led_eos_s3_1.c

@@ -0,0 +1,49 @@
+/*
+ * ==========================================================
+ *
+ *    Copyright (C) 2020 QuickLogic Corporation             
+ *    Licensed under the Apache License, Version 2.0 (the "License");
+ *    you may not use this file except in compliance with the License.
+ *    You may obtain a copy of the License at
+ * 		http://www.apache.org/licenses/LICENSE-2.0
+ *    Unless required by applicable law or agreed to in writing, software
+ *    distributed under the License is distributed on an "AS IS" BASIS,
+ *    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *    See the License for the specific language governing permissions and
+ *    limitations under the License.
+ *
+ *    File      : led_eos_s3_1.c
+ *    Purpose   : This is the driver for LED controller IP.
+ *    		                                                            
+ *                                                          
+ * ===========================================================
+ *
+ */
+
+#include <zephyr.h>
+#include <soc.h>
+#include <fpga_loader.h>
+#include "eos_s3_led1_ip.h"
+#include "eos_s3_led_config.h"
+
+static void config_ios()
+{
+	eos_s3_io_mux(FPGA_LED0_PAD, FPGA_LED0_PAD_CFG);
+	eos_s3_io_mux(FPGA_LED1_PAD, FPGA_LED1_PAD_CFG);
+	eos_s3_io_mux(FPGA_LED2_PAD, FPGA_LED2_PAD_CFG);
+
+	eos_s3_fbio_select(FPGA_LED0_PAD,FPGA_LED0_FBIO_SEL);
+	eos_s3_fbio_select(FPGA_LED1_PAD,FPGA_LED1_FBIO_SEL);
+	eos_s3_fbio_select(FPGA_LED2_PAD,FPGA_LED2_FBIO_SEL);
+
+}
+
+void program_fpga_ip()
+{
+	// Load bitstrem into FPGA
+	load_fpga(sizeof(axFPGABitStream),axFPGABitStream);
+
+	// Configure IOs
+	config_ios();
+}
+

samples/qf_helloworldhw/CMakeLists.txt

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.13.1)
+include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE)
+project(qf_helloworldhw)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
+#add_definitions( -DDBUG)

samples/qf_helloworldhw/README.rst

@@ -0,0 +1,31 @@
+.. _hello_world:
+
+Hello World
+###########
+
+Overview
+********
+The Hello World example can be used on Quick Feather board. 
+It prints 'Hello World' to the console using EOS S3 H/W UART and 
+blinks green on the board. It uses FPGA IP to blink the LED.
+
+Building and Running
+********************
+
+This project can be built and executed
+on Quick Feather as follows:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/qf_hello_worldhw
+   :host-os: unix
+   :board: quick feather
+   :goals: run
+   :compact:
+
+Sample Output
+=============
+
+.. code-block:: console
+
+    Hello World!
+

samples/qf_helloworldhw/prj.conf

@@ -0,0 +1 @@
+CONFIG_LED=y

samples/qf_helloworldhw/sample.yaml

@@ -0,0 +1,3 @@
+sample:
+  name: qf_helloworldhw Sample
+

samples/qf_helloworldhw/src/main.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+#include <device.h>
+#include <soc.h>
+
+void main(void)
+{
+    	printk("\n\n");
+    	printk( "##########################\n");
+    	printk( "Quicklogic Open Platform 2.0\n");
+    	printk( "SW Version: ");
+    	printk("OP2-QuickFeather-helloworldhw-app");
+    	printk( "\n" );
+    	printk( __DATE__ " " __TIME__ "\n" );
+    	printk( "##########################\n\n");
+
+	printk("Hello World!\n");
+
+	while (1);
+}

soc/arm/quicklogic_eos_s3/CMakeLists.txt

@@ -5,4 +5,5 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers)
 zephyr_sources(
   soc.c
   irq_handlers.c
+  fpga_loader.c
   )

soc/arm/quicklogic_eos_s3/Kconfig

@@ -13,3 +13,9 @@ config SOC_EOS_S3_FPGA
        bool
        help
          Enable on chip FPGA
+
+config EOS_S3_PROGRAM_FPGA
+	bool
+	help
+	  Enable programming the FPGA IP on EOS S3
+

soc/arm/quicklogic_eos_s3/Kconfig.defconfig

@@ -57,4 +57,10 @@ config SPI_EOS_S3
 
 endif # SPI
 
+if LED
+config EOS_S3_LED1
+	select EOS_S3_PROGRAM_FPGA
+	default y
+endif # LED
+
 endif # SOC_EOS_S3

soc/arm/quicklogic_eos_s3/fpga_loader.c

@@ -0,0 +1,153 @@
+/*==========================================================
+*                                                          
+*   Copyright 2020 QuickLogic
+*   
+*   Licensed under the Apache License, Version 2.0 (the "License");
+*   you may not use this file except in compliance with the License.
+*   You may obtain a copy of the License at
+*   
+*       http://www.apache.org/licenses/LICENSE-2.0
+*   
+*   Unless required by applicable law or agreed to in writing, software
+*   distributed under the License is distributed on an "AS IS" BASIS,
+*   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*   See the License for the specific language governing permissions and
+*   limitations under the License.
+*              
+*                                                          
+*    File   : fpga_loader.c
+*    Purpose: Contains functionality to load FPGA
+*                                                          
+*=========================================================*/
+
+#include <zephyr.h>
+#include <soc.h>
+#include <stdio.h>
+
+
+#define REG1                            (*(volatile uint32_t *)(0x40004610))
+#define REG2                            (*(volatile uint32_t *)(0x40004044))
+#define REG3                            (*(volatile uint32_t *)(0x4000404C))
+#define REG4                            (*(volatile uint32_t *)(0x40004064))
+
+#define REG5                            (*(volatile uint32_t *)(0x40004070))
+#define REG6                            (*(volatile uint32_t *)(0x4000411C))
+#define REG7                            (*(volatile uint32_t *)(0x40004054))
+#define REG8                            (*(volatile uint32_t *)(0x400047F8))
+
+#define REG9                            (*(volatile uint32_t *)(0x40014000))
+
+#define REG10                           (*(volatile uint32_t *)(0x400047F0))
+#define REG11                           (*(volatile uint32_t *)(0x400047F4))
+#define REG12                           (*(volatile uint32_t *)(0x40004088))
+#define REG13                           (*(volatile uint32_t *)(0x40004094))
+#define REG14                           (*(volatile uint32_t *)(0x400047F8))
+#define REG15                           (*(volatile uint32_t *)(0x40004040))
+#define REG16                           (*(volatile uint32_t *)(0x40004048))
+#define REG17                           (*(volatile uint32_t *)(0x4000404C))
+
+#define CFG_CTL_CFG_DATA                (*(volatile uint32_t *)(0x40014FFC))
+#define CFG_CTL_CFG_CTL                 (*(volatile uint32_t *)(0x40014000))
+
+static void enable_clocks()
+{
+	PMU->FFE_FB_PF_SW_WU = PMU_FFE_FB_PF_SW_WU_PF_WU
+		| PMU_FFE_FB_PF_SW_WU_FB_WU
+		| PMU_FFE_FB_PF_SW_WU_FFE_WU;
+	CRU->FB_SW_RESET = FB_C21_DOMAIN_SW_RESET | FB_C16_DOMAIN_SW_RESET
+		| FB_C09_DOMAIN_SW_RESET | FB_C02_DOMAIN_SW_RESET;
+
+	CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_0_ON | C02_CLK_GATE_PATH_1_ON
+		| C02_CLK_GATE_PATH_2_ON;
+
+	CRU->C08_X1_CLK_GATE = C08_X1_CLK_GATE_PATH_1_ON
+		| C08_X1_CLK_GATE_PATH_2_ON;
+
+	CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON;
+
+	CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_ON;
+
+	CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_ON | C09_CLK_GATE_PATH_2_ON;
+}
+
+/*************************************************************
+ *
+ *  Load FPGA from in memory description
+ *
+ *************************************************************/
+
+int load_fpga(uint32_t img_size,uint32_t* image_ptr)
+{
+	unsigned int    i = 0;
+	uint32_t        chunk_cnt=0;
+	volatile uint32_t   *gFPGAPtr = (volatile uint32_t*)image_ptr;
+
+	*((volatile unsigned int*) 0x40004c4c) = 0x00000180;
+
+	enable_clocks();
+
+	// Configuration of CFG_CTRL for writes
+	CFG_CTL_CFG_CTL = 0x0000bdff ;
+	// wait some time for fpga to get reset pulse
+	for (i=0;i<50; i++) {
+		PMU->GEN_PURPOSE_1  = i << 4;
+	}
+
+	REG8 = 0x10;
+	REG8 = 0x20;
+	REG8 = 0x30;
+	REG8 = 0x40;
+	REG8 = 0x50;
+	REG8 = 0x60;
+	REG8 = 0x70;
+	REG8 = 0x80;
+
+	REG9 = 0xBDFF;
+
+	REG8 = 0x10;
+	REG8 = 0x20;
+	REG8 = 0x30;
+	REG8 = 0x40;
+	REG8 = 0x50;
+	REG8 = 0x60;
+	REG8 = 0x70;
+	REG8 = 0x80;
+
+
+	for(chunk_cnt=0;chunk_cnt<(img_size/4);chunk_cnt++)
+		CFG_CTL_CFG_DATA = gFPGAPtr[chunk_cnt];
+
+	// wait some time for fpga to get reset pulse
+	for (i=0;i<50; i++) {
+		PMU->GEN_PURPOSE_1  = i << 4;
+	}
+
+	CFG_CTL_CFG_CTL = 0x0; // exit config mode
+	REG10 = 0;
+
+
+	REG11 = 0;
+
+
+
+	REG12 = 0;
+	REG13 = 0;
+	REG14 = 0x90;
+
+
+	PMU->GEN_PURPOSE_0 = 0x0; //set APB_FB_EN = 0 for normal mode
+
+	// required wait time before releasing LTH_ENB
+	for (i=0;i<500; i++) {
+		PMU->GEN_PURPOSE_1  = i << 4;
+	}
+
+	//release isolation - LTH_ENB
+	PMU->FB_ISOLATION = 0x0;
+	*((volatile unsigned int*) 0x40004c4c) = 0x000009a0;
+
+	printf("FPGA is programmed\r\n");
+
+	return 1;
+
+}