FPGA Design Build System v1.0.0
Main Targets: help - shows this menu setup - sets up project structure and FuseSoC clean - removes build files veryclean - removes all generated files
FuseSoC Targets: list_cores - lists all available cores core_info_% - shows info for specific core
Simulation Targets: sim_% - simulates design using Verilator view_% - opens waveform for design
Synthesis Targets: syn_% - synthesizes design using Yosys
Analysis Targets: lint_% - lints design using Verilator
Module Generation: module_% - creates new module with core fileModule Generation: module_% - creates new module with core file