Skip to content

Commit

Permalink
Documentation Update: Ensure consistency across project
Browse files Browse the repository at this point in the history
        Create Roalogic version of theme styling

        Add PDF download link to datasheet markdown

        Set LaTex layout dimensions for PDF output - recreate PDF

        Update IP naming for consistency

        Clean up markdown:

        * Set defaults in config.yml
        * Remove redundant frontmatter
        * Update markdown to use GitHub repo metadata - to ensure consistency

        Add test page for debug purposes

        Clean up output files

        Enable access to GitHub metadata
  • Loading branch information
sphardy committed Nov 18, 2020
1 parent 85222eb commit a1f41d1
Show file tree
Hide file tree
Showing 21 changed files with 527 additions and 206 deletions.
3 changes: 1 addition & 2 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@
.ruby-version
docs/build
docs/*.sh
docs/tex/build
docs/_site
6 changes: 3 additions & 3 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
![Roa Logic Hdr][]

# AHB-Lite Multilayer Switch
# AHB-Lite Multi-layer Interconnect Switch

The Roa Logic *AHB-Lite Multi-layer Interconnect* is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It allows a virtually unlimited number of AHB-Lite bus masters and slaves to be connected without the need of bus arbitration to be implemented by the bus masters. Instead, slave side arbitration is implemented for each slave port within the core.
The Roa Logic *AHB-Lite Multi-layer Interconnect Switch* is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It allows a virtually unlimited number of AHB-Lite bus masters and slaves to be connected without the need of bus arbitration to be implemented by the bus masters. Instead, slave side arbitration is implemented for each slave port within the core.

The Multi-layer Interconnect supports priority and round-robin based arbitration when multiple bus masters request access to the same slave port. Arbitration typically completes within 1 clock cycle
The Interconnect supports priority and round-robin based arbitration when multiple bus masters request access to the same slave port. Arbitration typically completes within 1 clock cycle

![System Diagram][]

Expand Down
3 changes: 3 additions & 0 deletions docs/Gemfile
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
source 'https://rubygems.org'
gem 'dotenv'
gem 'github-pages', group: :jekyll_plugins
7 changes: 4 additions & 3 deletions docs/_config.yml
Original file line number Diff line number Diff line change
@@ -1,11 +1,13 @@
title: AHB-Lite Multi-Layer Switch
title: AHB-Lite Multi-Layer Interconnect Switch
description: Parameterised AHB-Lite Multi-layer Interconnect Switch

theme: jekyll-theme-dinky
show_downloads: true
show_license: true
license: Non-Commercial License

repository: RoaLogic/ahb3lite_interconnect

url: https://roalogic.github.io
baseurl: /ahb3lite_interconnect

Expand All @@ -19,7 +21,6 @@ exclude:
- "*.sh" # Ignore any scripts
- "/assets/img/*.pdf" # PDF images used for PDF Datasheet
- "/assets/img/*.eps" # EPS images used for PDF Datasheet
- build # Temp build folder for PDF Datasheet
- markdown # Markdown Datasheet generation scripts
- pkg # PDF Datasheet layout definition
- tex # Original source texfiles
Expand All @@ -32,5 +33,5 @@ defaults:
path : ""
type : pages
values:
layout : roalogic
layout : roalogic # Use custom layout for *all* pages
author : Roa Logic
3 changes: 1 addition & 2 deletions docs/_layouts/roalogic.html
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ <h1 class="header">{{ site.title | default: site.github.repository_name }}</h1>
</ul>

{% if site.show_license %}
<p class="header">License Terms:<br><a class="header name" href="{{ '/LICENSE' | relative_url}}">{{ site.license }}</a></p>
<p class="header">License Terms:<br><a class="header name" href="{{ '/license' | relative_url}}">{{ site.license }}</a></p>
{% endif %}

{% if site.github.is_user_page %}
Expand All @@ -52,7 +52,6 @@ <h1 class="header">{{ site.title | default: site.github.repository_name }}</h1>
</section>

<footer>
<!--p class="logo"><a href="{{ site.github.owner_url }}"><img src="{{ 'assets/img/RoaLogicLogo.png' | relative_url}}"></a></p-->
<p align=center><small>Hosted on <a href="https://pages.github.com">GitHub Pages</a></small></p>
</footer>

Expand Down
28 changes: 16 additions & 12 deletions docs/_pages/index.md
Original file line number Diff line number Diff line change
@@ -1,12 +1,11 @@
---
title: Roa Logic AHB-Lite Multilayer Switch Documentation
author: Roa Logic
title: Documentation
permalink: /
---

# AHB-Lite Multilayer Switch
# {{site.title}}

The Roa Logic *AHB-Lite Multi-layer Interconnect* is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It allows a virtually unlimited number of AHB-Lite bus masters and slaves to be connected without the need of bus arbitration to be implemented by the bus masters. Instead, slave side arbitration is implemented for each slave port within the core.
The Roa Logic *AHB-Lite Multi-layer Interconnect Switch* is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It allows a virtually unlimited number of AHB-Lite bus masters and slaves to be connected without the need of bus arbitration to be implemented by the bus masters. Instead, slave side arbitration is implemented for each slave port within the core.

The Multi-layer Interconnect supports priority and round-robin based arbitration when multiple bus masters request access to the same slave port. Arbitration typically completes within 1 clock cycle

Expand Down Expand Up @@ -39,20 +38,25 @@ Released under the RoaLogic [Non-Commercial License][NC License]

## Dependencies

This release requires the ahb3lite package found here: [https://github.com/RoaLogic/ahb3lite_pkg][ahb3lite pkg]
This release requires the Roa Logic [ahb3lite package][ahb3lite pkg]

[^1]: The number of bus masters and slaves is physically limited by the timing requirements of the design.

[GitHub Pages]: https://roalogic.github.io/ahb3lite_interconnect/ "GitHub Pages Documentation"
[System Diagram]: {{site.baseurl}}{% link assets/img/ahb-lite-switch-sys.png %}
"Example Interconnect System"

[ahb3lite pkg]: https://github.com/RoaLogic/ahb3lite_pkg "ahb3lite submodule"
[HTML Datasheet]: {{site.baseurl}}/{{ site.github.repository_name | append: "_datasheet.html" }}
"AHB3Lite Interconnect Datasheet (HTML)"

[System Diagram]: {{site.baseurl}}{% link assets/img/ahb-lite-switch-sys.png %} "Example Interconnect System"
[PDF Datasheet]: {{site.baseurl}}/{{site.github.repository_name | append: "_datasheet.pdf"}}
"AHB3Lite Interconnect Datasheet (PDF)"

[HTML Datasheet]: {{site.baseurl}}{% link ahb3lite_interconnect_datasheet.md %} "AHB3Lite Interconnect Datasheet (HTML)"
[NC License]: {{site.baseurl}}{% link _pages/license.md %}
"Non-Commercial License"

[PDF Datasheet]: {{site.baseurl}}{% link ahb3lite_interconnect_datasheet.pdf %} "AHB3Lite Interconnect Datasheet (PDF)"
[ReadMe]: {{site.baseurl}}{% link readme.md %}

[NC License]: {{site.baseurl}}{% link _pages/license.md %} "Non-Commercial License"

[ReadMe]: {{site.baseurl}}{% link readme.md %}
[GitHub Pages]: {{site.github.url}} "GitHub Pages Documentation"

[ahb3lite pkg]: {{site.github.owner_url}}/ahb3lite_pkg "ahb3lite submodule"
2 changes: 1 addition & 1 deletion docs/_pages/license.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
---
title: Non-Commercial License Agreement
title: License
permalink: /license/
---
# Non-Commercial License Agreement
Expand Down
16 changes: 16 additions & 0 deletions docs/_pages/test.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
---
title: Test & Debug Page
permalink: /test/
---
# {{page.title}}

## GitHub Metadata Test

Owner: {{site.github.owner_name}}

Public Repos:
{% for repository in site.github.public_repositories %}
* [{{ repository.name }}]({{ repository.html_url }})
{% endfor %}

---
Loading

0 comments on commit a1f41d1

Please sign in to comment.