Docs/v1.2 (#8)

* Update Gem file and .gitignore

* Update metadata / title info / history

* Add Recursive Function Support documentation

* Update release date

* Build PDF & Markdown datasheets

* Fix footnote reference in README

.gitignore

@@ -1 +1,2 @@
 docs/build
+.ruby-version

DATASHEET.md

@@ -9,7 +9,7 @@ Author: Roa Logic
 
 -   [Introduction](#introduction)
 -   [Specifications](#specifications)
--   [Configurations](#configurations)
+-   [Configuration](#configuration)
 -   [Interfaces](#interfaces)
 -   [Resources](#resources)
 -   [Revision History](#revision-history)
@@ -126,7 +126,7 @@ Similarly since there is no other slave on the Slave Bus, the Slave Port’s `HR
 
 The number of Slave Ports is specified by the `SLAVES` parameter.
 
-## Configurations
+## Configuration
 
 ### Introduction
 
@@ -177,6 +177,18 @@ Setting an `ERROR_ON_SLAVE_MASK[]` bit to ’0’ indicates that an AHB error re
 
 The default value of `ERROR_ON_SLAVE_MASK[]` is the bitwise inverse of `SLAVE_MASK[]` - i.e. inv(`SLAVE_MASK[]`). If `SLAVE_MASK[]` is assigned a value, then `ERROR_ON_SLAVE_MASK[]` is by default inv(`SLAVE_MASK[]`).
 
+### Core Macros
+
+| Macro                           | Description                       |
+|:--------------------------------|:----------------------------------|
+| `RECURSIVE_FUNCTIONS_SUPPORTED` | Enable use of recursive functions |
+
+#### RECURSIVE\_FUNCTIONS\_SUPPORTED
+
+Recursive functions and modules are used within the verilog source code. However EDA tools vary in their support for recursion, with some supporting recursive functions, whereas others support recursive modules or both. For example, Intel Quartus v19.1 and earlier supports recursive modules, but not recursive functions.
+
+To accomodate these toolchain differences, recursive modules are the default method used for implementation. However recursive functions may instead be enabled by setting the synthesis macro `RECURSIVE_FUNCTIONS_SUPPORTED`
+
 ## Interfaces
 
 ### Global Signals
@@ -473,7 +485,6 @@ Below are some example implementations when targeting the Altera Cyclone-V famil
 |:-----------:|:--------:|:----------------------------------------|
 | 13-Oct-2017 |    1.0   | Initial Release                         |
 | 16-Sep-2019 |    1.1   | Updated to add `SLAVE_MASK[]` Parameter |
-|             |          |                                         |
-|             |          |                                         |
+| 04-Nov-2020 |    1.2   | Add Recursive Function support          |
 
 [1] The number of Bus Masters and Slaves is physically limited by the timing requirements.

Gemfile

@@ -0,0 +1,2 @@
+source 'https://rubygems.org'
+gem 'github-pages', group: :jekyll_plugins

README.md

@@ -16,7 +16,7 @@ The Multi-layer Interconnect supports Priority and Round-Robin based arbitration
 
 - AMBA AHB-Lite Compatible
 - Fully parameterized
-- Unlimited number of Bus Masters and Slaves[[1\]](https://roalogic.com/portfolio/ahb-lite-multilayer-switch/#_ftn1)
+- Unlimited number of Bus Masters and Slaves[^1]
 - Slave side arbitration
 - Priority and Round-Robin based arbitration
 - Slave Port address decoding
@@ -32,3 +32,5 @@ Released under the RoaLogic [Non-Commercial License](/LICENSE.md)
 ## Dependencies
 
 This release requires the ahb3lite package found here: [https://github.com/RoaLogic/ahb3lite_pkg](https://github.com/RoaLogic/ahb3lite_pkg)
+
+[^1]: The number of Bus Masters and Slaves is physically limited by the timing requirements of the design.

docs/tex/configuration.tex

@@ -1,4 +1,4 @@
-\chapter{Configurations}\label{configurations}
+\chapter{Configuration}\label{configuration}
 
 
 \section{Introduction}\label{introduction-1}
@@ -72,3 +72,21 @@ \subsection{ERROR\_ON\_SLAVE\_MASK[ ]}\label{error_on_slave_mask}
 be generated if the master is masked from accessing the corresponding slave.
 
 The default value of \texttt{ERROR\_ON\_SLAVE\_MASK[\,]} is the bitwise inverse of \texttt{SLAVE\_MASK[\,]} - i.e. inv(\texttt{SLAVE\_MASK[\,]}). If \texttt{SLAVE\_MASK[\,]} is assigned a value, then \texttt{ERROR\_ON\_SLAVE\_MASK[\,]} is by default inv(\texttt{SLAVE\_MASK[\,]}).
+
+\section{Core Macros}\label{core-macros}
+
+\begin{longtable}[]{@{}ll@{}}
+\toprule
+Macro & Description\tabularnewline
+\midrule
+\endhead
+\texttt{RECURSIVE\_FUNCTIONS\_SUPPORTED} & Enable use of recursive functions \tabularnewline
+\bottomrule
+\caption{Core Macros}
+\end{longtable}
+
+\subsection{RECURSIVE\_FUNCTIONS\_SUPPORTED}\label{recursive_functions_supported}
+
+Recursive functions and modules are used within the verilog source code. However EDA tools vary in their support for recursion, with some supporting recursive functions, whereas others support recursive modules or both. For example, Intel Quartus v19.1 and earlier supports recursive modules, but not recursive functions. 
+
+To accomodate these toolchain differences, recursive modules are the default method used for implementation. However recursive functions may instead be enabled by setting the synthesis macro \texttt{RECURSIVE\_FUNCTIONS\_SUPPORTED}

docs/tex/history.tex

@@ -10,8 +10,7 @@ \chapter{Revision History}
 	\endhead
 		13-Oct-2017 & 1.0 & Initial Release\\
 		16-Sep-2019 & 1.1 & Updated to add \texttt{SLAVE\_MASK[\,]} Parameter\\
-		              &     & \\
-		              &     & \\
+		04-Nov-2020 & 1.2 & Add Recursive Function support\\
 	\bottomrule
 	\caption{Revision History}
 	\label{tab:REVS}

docs/tex/setup.tex

@@ -8,8 +8,8 @@
 \title{AHB-Lite Multilayer Interconnect}
 \heading{AHB-Lite Multilayer Interconnect}
 \author{Roa Logic}
-\date{16-Sep-2019}
-\version{1.1}
+\date{04-Nov-2020}
+\version{1.2}
 \doctype{Datasheet}
 \project{https://roalogic.github.io/ahb3lite\_interconnect}
 \author{Paul Hardy}