Cleaned up start.s files

Shadowtrance · Jun 27, 2016 · efa2093 · efa2093
1 parent 6c19e9b
commit efa2093
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Showing 2 changed files with 14 additions and 18 deletions.
diff --git a/source/abstraction/a9-start.s b/source/abstraction/a9-start.s
@@ -28,9 +28,7 @@ _start:
     ldr r5, =0x20000035	@ 20000000 128M
     ldr r6, =0x1FF00027	@ 1FF00000 1M
     ldr r7, =0x1800002D	@ 18000000 8M
-    mov r10, #0x25
-    mov r11, #0x25
-    mov r12, #0x25
+    mov r8, #0x25
     mcr p15, 0, r0, c6, c0, 0
     mcr p15, 0, r1, c6, c1, 0
     mcr p15, 0, r2, c6, c2, 0
@@ -39,9 +37,9 @@ _start:
     mcr p15, 0, r5, c6, c5, 0
     mcr p15, 0, r6, c6, c6, 0
     mcr p15, 0, r7, c6, c7, 0
-    mcr p15, 0, r10, c3, c0, 0	@ Write bufferable 0, 2, 5
-    mcr p15, 0, r11, c2, c0, 0	@ Data cacheable 0, 2, 5
-    mcr p15, 0, r12, c2, c0, 1	@ Inst cacheable 0, 2, 5
+    mcr p15, 0, r8, c3, c0, 0	@ Write bufferable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 0	@ Data cacheable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 1	@ Inst cacheable 0, 2, 5
 
     @ Enable caches
     mrc p15, 0, r4, c1, c0, 0  @ read control register
@@ -58,9 +56,9 @@ _start:
     mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
 
     @ Fixes mounting of SDMC
-	ldr r0, =0x10000020
-	mov r1, #0x340
-	str r1, [r0]
+    ldr r0, =0x10000020
+    mov r1, #0x340
+    str r1, [r0]
 
     bl main
 

diff --git a/source/abstraction/gw-start.s b/source/abstraction/gw-start.s
@@ -58,9 +58,7 @@ _start:
     ldr r5, =0x20000035	@ 20000000 128M
     ldr r6, =0x1FF00027	@ 1FF00000 1M
     ldr r7, =0x1800002D	@ 18000000 8M
-    mov r10, #0x25
-    mov r11, #0x25
-    mov r12, #0x25
+    mov r8, #0x25
     mcr p15, 0, r0, c6, c0, 0
     mcr p15, 0, r1, c6, c1, 0
     mcr p15, 0, r2, c6, c2, 0
@@ -69,9 +67,9 @@ _start:
     mcr p15, 0, r5, c6, c5, 0
     mcr p15, 0, r6, c6, c6, 0
     mcr p15, 0, r7, c6, c7, 0
-    mcr p15, 0, r10, c3, c0, 0	@ Write bufferable 0, 2, 5
-    mcr p15, 0, r11, c2, c0, 0	@ Data cacheable 0, 2, 5
-    mcr p15, 0, r12, c2, c0, 1	@ Inst cacheable 0, 2, 5
+    mcr p15, 0, r8, c3, c0, 0	@ Write bufferable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 0	@ Data cacheable 0, 2, 5
+    mcr p15, 0, r8, c2, c0, 1	@ Inst cacheable 0, 2, 5
 
     @ Enable caches
     mrc p15, 0, r4, c1, c0, 0  @ read control register
@@ -88,9 +86,9 @@ _start:
     mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
 
     @ Fixes mounting of SDMC
-	ldr r0, =0x10000020
-	mov r1, #0x340
-	str r1, [r0]
+    ldr r0, =0x10000020
+    mov r1, #0x340
+    str r1, [r0]
 
     ldr sp,=0x22160000
     ldr    r3, =main