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advance hkp3c SGMII not yet functional
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| ## fpgaTop.xdc for hdmi output application | ||
| ## KC705 Rev C XDC | ||
| ## Shepard Siegel for Atomic Rules LLC | ||
| ## 2013-01-03 cloned from ucf | ||
| ## 2013-01-26 Added FMC LPC pads | ||
| ## 2013-02-06 Added GMII IO Constraints | ||
| ## 2012-02-17 Hotline IP debugging | ||
| ## 2012-09-03 (hkp3c) SGMII | ||
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| # 200 MHz XO... | ||
| set_property PACKAGE_PIN AD12 [get_ports sys0_clkp] | ||
| set_property PACKAGE_PIN AD11 [get_ports sys0_clkn] | ||
| set_property IOSTANDARD LVDS [get_ports sys0_clkp] | ||
| set_property IOSTANDARD LVDS [get_ports sys0_clkn] | ||
| create_clock -period 5.000 -name sys0_clkp -waveform {0.000 2.500} [get_ports sys0_clkp] | ||
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| # 125 MHz GTX Clock... | ||
| set_property PACKAGE_PIN G8 [get_ports sys1_clkp] | ||
| set_property PACKAGE_PIN G7 [get_ports sys1_clkn] | ||
| create_clock -period 8.000 -name sys1_clkp -waveform {0.000 4.000} [get_ports sys1_clkp] | ||
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| set_property PACKAGE_PIN AB7 [get_ports sys0_rst] | ||
| set_property IOSTANDARD LVCMOS15 [get_ports sys0_rst] | ||
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| ## GbE SGMII | ||
| set_property PACKAGE_PIN J4 [get_ports sgmii_txp] | ||
| set_property PACKAGE_PIN J3 [get_ports sgmii_txn] | ||
| set_property PACKAGE_PIN H6 [get_ports sgmii_rxp] | ||
| set_property PACKAGE_PIN H5 [get_ports sgmii_rxn] | ||
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| ## PHY Reset.. | ||
| set_property PACKAGE_PIN L20 [get_ports gmii_rstn] | ||
| set_property IOSTANDARD LVCMOS25 [get_ports gmii_*] | ||
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| # LEDs | ||
| set_property PACKAGE_PIN AB8 [get_ports {led[0]}] | ||
| set_property PACKAGE_PIN AA8 [get_ports {led[1]}] | ||
| set_property PACKAGE_PIN AC9 [get_ports {led[2]}] | ||
| set_property PACKAGE_PIN AB9 [get_ports {led[3]}] | ||
| set_property PACKAGE_PIN AE26 [get_ports {led[4]}] | ||
| set_property PACKAGE_PIN G19 [get_ports {led[5]}] | ||
| set_property PACKAGE_PIN E18 [get_ports {led[6]}] | ||
| set_property PACKAGE_PIN F16 [get_ports {led[7]}] | ||
| set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}] | ||
| set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}] | ||
| set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}] | ||
| set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}] | ||
| set_property IOSTANDARD LVCMOS25 [get_ports {led[4]}] | ||
| set_property IOSTANDARD LVCMOS25 [get_ports {led[5]}] | ||
| set_property IOSTANDARD LVCMOS25 [get_ports {led[6]}] | ||
| set_property IOSTANDARD LVCMOS25 [get_ports {led[7]}] | ||
| set_property SLEW SLOW [get_ports {led[*]}] | ||
| set_property DRIVE 4 [get_ports {led[*]}] | ||
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| # Asynchronous Clock Groups... | ||
| set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sys0_clkp] -group [get_clocks -include_generated_clocks sys1_clkp] | ||
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| // (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. | ||
| // | ||
| // This file contains confidential and proprietary information | ||
| // of Xilinx, Inc. and is protected under U.S. and | ||
| // international copyright and other intellectual property | ||
| // laws. | ||
| // | ||
| // DISCLAIMER | ||
| // This disclaimer is not a license and does not grant any | ||
| // rights to the materials distributed herewith. Except as | ||
| // otherwise provided in a valid license issued to you by | ||
| // Xilinx, and to the maximum extent permitted by applicable | ||
| // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND | ||
| // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES | ||
| // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING | ||
| // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- | ||
| // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and | ||
| // (2) Xilinx shall not be liable (whether in contract or tort, | ||
| // including negligence, or under any other theory of | ||
| // liability) for any loss or damage of any kind or nature | ||
| // related to, arising under or in connection with these | ||
| // materials, including for any direct, or any indirect, | ||
| // special, incidental, or consequential loss or damage | ||
| // (including loss of data, profits, goodwill, or any type of | ||
| // loss or damage suffered as a result of any action brought | ||
| // by a third party) even if such damage or loss was | ||
| // reasonably foreseeable or Xilinx had been advised of the | ||
| // possibility of the same. | ||
| // | ||
| // CRITICAL APPLICATIONS | ||
| // Xilinx products are not designed or intended to be fail- | ||
| // safe, or for use in any application requiring fail-safe | ||
| // performance, such as life-support or safety devices or | ||
| // systems, Class III medical devices, nuclear facilities, | ||
| // applications related to the deployment of airbags, or any | ||
| // other applications that could lead to death, personal | ||
| // injury, or severe property or environmental damage | ||
| // (individually and collectively, "Critical | ||
| // Applications"). Customer assumes the sole risk and | ||
| // liability of any use of Xilinx products in Critical | ||
| // Applications, subject only to applicable laws and | ||
| // regulations governing limitations on product liability. | ||
| // | ||
| // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS | ||
| // PART OF THIS FILE AT ALL TIMES. | ||
| // | ||
| // DO NOT MODIFY THIS FILE. | ||
|
|
||
| // IP VLNV: xilinx.com:ip:gig_ethernet_pcs_pma:13.0 | ||
| // IP Revision: 0 | ||
|
|
||
| // The following must be inserted into your Verilog file for this | ||
| // core to be instantiated. Change the instance name and port connections | ||
| // (in parentheses) to your own signal names. | ||
|
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| //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG | ||
| gig_ethernet_pcs_pma_0 your_instance_name ( | ||
| .gtrefclk(gtrefclk), // input gtrefclk | ||
| .txn(txn), // output txn | ||
| .txp(txp), // output txp | ||
| .rxn(rxn), // input rxn | ||
| .rxp(rxp), // input rxp | ||
| .txoutclk(txoutclk), // output txoutclk | ||
| .resetdone(resetdone), // output resetdone | ||
| .mmcm_locked(mmcm_locked), // input mmcm_locked | ||
| .userclk(userclk), // input userclk | ||
| .userclk2(userclk2), // input userclk2 | ||
| .independent_clock_bufg(independent_clock_bufg), // input independent_clock_bufg | ||
| .drpaddr_in(drpaddr_in), // input [8 : 0] drpaddr_in | ||
| .drpclk_in(drpclk_in), // input drpclk_in | ||
| .drpdi_in(drpdi_in), // input [15 : 0] drpdi_in | ||
| .drpdo_out(drpdo_out), // output [15 : 0] drpdo_out | ||
| .drpen_in(drpen_in), // input drpen_in | ||
| .drprdy_out(drprdy_out), // output drprdy_out | ||
| .drpwe_in(drpwe_in), // input drpwe_in | ||
| .pma_reset(pma_reset), // input pma_reset | ||
| .sgmii_clk_r(sgmii_clk_r), // output sgmii_clk_r | ||
| .sgmii_clk_f(sgmii_clk_f), // output sgmii_clk_f | ||
| .sgmii_clk_en(sgmii_clk_en), // output sgmii_clk_en | ||
| .gmii_txd(gmii_txd), // input [7 : 0] gmii_txd | ||
| .gmii_tx_en(gmii_tx_en), // input gmii_tx_en | ||
| .gmii_tx_er(gmii_tx_er), // input gmii_tx_er | ||
| .gmii_rxd(gmii_rxd), // output [7 : 0] gmii_rxd | ||
| .gmii_rx_dv(gmii_rx_dv), // output gmii_rx_dv | ||
| .gmii_rx_er(gmii_rx_er), // output gmii_rx_er | ||
| .gmii_isolate(gmii_isolate), // output gmii_isolate | ||
| .configuration_vector(configuration_vector), // input [4 : 0] configuration_vector | ||
| .speed_is_10_100(speed_is_10_100), // input speed_is_10_100 | ||
| .speed_is_100(speed_is_100), // input speed_is_100 | ||
| .status_vector(status_vector), // output [15 : 0] status_vector | ||
| .reset(reset), // input reset | ||
| .signal_detect(signal_detect) // input signal_detect | ||
| ); | ||
| // INST_TAG_END ------ End INSTANTIATION Template --------- | ||
|
|
||
| // You must compile the wrapper file gig_ethernet_pcs_pma_0.v when simulating | ||
| // the core, gig_ethernet_pcs_pma_0. When compiling the wrapper file, be sure to | ||
| // reference the Verilog simulation library. | ||
|
|
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> | ||
| <spirit:vendor>xilinx.com</spirit:vendor> | ||
| <spirit:library>xci</spirit:library> | ||
| <spirit:name>unknown</spirit:name> | ||
| <spirit:version>1.0</spirit:version> | ||
| <spirit:componentInstances> | ||
| <spirit:componentInstance> | ||
| <spirit:instanceName>gig_ethernet_pcs_pma_0</spirit:instanceName> | ||
| <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gig_ethernet_pcs_pma" spirit:version="13.0"/> | ||
| <spirit:configurableElementValues> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">gig_ethernet_pcs_pma_0</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STANDARD">SGMII</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHYSICAL_INTERFACE">Transceiver</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MANAGEMENT_INTERFACE">false</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_NEGOTIATION">false</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRANSCEIVER_TILE">A</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SGMII_MODE">10_100_1000</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SGMII_PHY_MODE">false</spirit:configurableElementValue> | ||
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| <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMAC_IF_TEMAC">TEMAC</spirit:configurableElementValue> | ||
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| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_TRANSIENT_DIR">.</spirit:configurableElementValue> | ||
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| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_SGMII">true</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TRANSCEIVER">true</spirit:configurableElementValue> | ||
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| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LVDS">false</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AN">false</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MDIO">false</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SGMII_PHY_MODE">false</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DYNAMIC_SWITCHING">false</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRANSCEIVER_MODE">A</spirit:configurableElementValue> | ||
| <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SGMII_FABRIC_BUFFER">true</spirit:configurableElementValue> | ||
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| <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue> | ||
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| <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> | ||
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