n210 DNA and ICAP insertion

Makefile

@@ -659,6 +659,7 @@ platform_n210: $(OBJ)
 		-p $(BSVDIRS):lib:+ \
 		-D USE_NDW1 \
 		-D USE_DEBUGLOGIC \
+		-D HAS_DEVICE_DNA \
 		-D USE_SRLFIFO \
 		-D SPARTAN \
 		-verilog-filter basicinout $(BSVTOP)/$(P_N210).bsv

bin/send_dcp_dna.py

@@ -0,0 +1,36 @@
+#!/usr/bin/env python2.7
+# send_dcp.py - Send a DCP packet
+# Copyright (c) 2012 Atomic Rules LLC - ALL Rights Reserved
+
+import optparse
+import os
+import re
+import subprocess
+import sys
+import time
+
+from scapy.all import *
+
+def main(argv):
+  print """Hello from %s""" % (prog_name)
+  p = Ether()
+  p.src  = '00:26:E1:01:01:00'   # Linux Host Source MAC Address
+  p.dst  = '00:0A:35:42:01:00'   # Xilinx FPGA Dest MAC Address
+  p.type = 0xF040                # EtherType TCP
+  #p.payload = "\x00\x0A\x00\x00\x0F\x05\x80\x00\x00\x01"                    # 10B NOP
+  #p.payload = "\x00\x0E\x00\x00\x1F\x06\x00\x00\x00\x24\x00\x00\x00\x02"    # 14B Write 0x24 with 0x00000002
+  #p.payload = "\x00\x0A\x00\x00\x2F\x07\x00\x00\x00\x24"                     # 10B Read 0x24
+
+  p.payload = "\x00\x0A\x00\x00\x2F\x07\x00\x00\x00\x50"                     # 10B Read 
+  print "Sending packet..."
+  r = srp(p, iface="eth1")
+  #print r
+  #print 'r is a ' + str(type(r))
+  p.payload = "\x00\x0A\x00\x00\x2F\x07\x00\x00\x00\x54"                     # 10B Read 
+  print "Sending packet..."
+  r = srp(p, iface="eth1")
+
+
+prog_name = os.path.basename(sys.argv[0])
+if __name__ == '__main__':
+    main(sys.argv)

bsv/dev/ICAP.bsv

@@ -20,6 +20,21 @@ interface ICAP;
    method Action     csb(Bool i);       // False for Chip Select
 endinterface: ICAP
 
+import "BVI" ICAP_SPARTAN3A =
+module vICAP_S3A (ICAP);
+
+   default_clock clk(CLK);
+   default_reset no_reset;
+
+   method O         configOut;
+   method BUSY      busy;
+   method configIn (I)      enable((*inhigh*)en0);
+   method rdwrb    (WRITE)  enable((*inhigh*)en1);
+   method csb      (CE)     enable((*inhigh*)en2);
+
+   schedule (configOut, busy, configIn, rdwrb, csb) CF (configOut, busy, configIn, rdwrb, csb); 
+endmodule: vICAP_S3A
+
 import "BVI" ICAP_VIRTEX5 =
 module vICAP_V5 (ICAP);
 
@@ -70,9 +85,23 @@ function Bit#(n) reverseBitsInBytes(Bit#(n) a) provisos (Mul#(8,b,n));
   return pack(vBytes);
 endfunction
 
-module mkICAP (ICAPIfc);
+module mkICAP#(String icapPrim) (ICAPIfc);
+
+/*
+  ICAP  icap = ?;
+  case (icapPrim)
+    "S3A"    :  icap <- vICAP_S3A;
+    "V5"     :  icap <- vICAP_V5;
+    "V6"     :  icap <- vICAP_V6;
+    default  :  icap <- vICAP_V6;
+  endcase
+*/
+`ifdef SPARTAN
+  ICAP icap <- vICAP_S3A;
+`else
+  ICAP icap <- vICAP_V6;
+`endif
 
-  ICAP                 icap      <- vICAP_V6;
   FIFOF#(Bit#(32))     cinF      <- mkFIFOF;
   FIFOF#(Bit#(32))     coutF     <- mkFIFOF;
   Reg#(Bool)           icapCs    <- mkDReg(False);  // default deselected

bsv/top/FTop_kc705.bsv

@@ -94,7 +94,7 @@ module mkFTop_kc705#(Clock sys0_clkp, Clock sys0_clkn, Reset sys0_rstn,
   Vector#(Nwci_ftop, WciEM) vWci = ctop.wci_m;  // expose WCI from CTop
 
   // FTop Level board-specific workers..
-  //ICAPWorkerIfc    icap     <- mkICAPWorker(True,True,                      clocked_by p125Clk , reset_by(vWci[0].mReset_n));
+  //ICAPWorkerIfc    icap     <- mkICAPWorker("X7",True,                      clocked_by p125Clk , reset_by(vWci[0].mReset_n));
   //FlashWorkerIfc   flash0   <- mkFlashWorker(True,                          clocked_by p125Clk , reset_by(vWci[1].mReset_n));
   GbeWorkerIfc     gbe0   <- mkGbeWorker(True,gmii_rx_clk, sys1_clk, sys1_rst, clocked_by p125Clk , reset_by(vWci[2].mReset_n));
   WSICaptureWorker4BIfc cap0  <- mkWSICaptureWorker(True,                      clocked_by p125Clk , reset_by(vWci[3].mReset_n));

bsv/top/FTop_ml605.bsv

@@ -105,7 +105,7 @@ module mkFTop_ml605#(Clock sys0_clkp,     Clock sys0_clkn,      // 200 MHz Board
   Vector#(Nwci_ftop, WciEM) vWci = ctop.wci_m;  // expose WCI from CTop
 
   // FTop Level board-specific workers..
-//ICAPWorkerIfc    icap   <- mkICAPWorker(True,True,                           clocked_by p125Clk , reset_by(vWci[0].mReset_n));
+//ICAPWorkerIfc    icap   <- mkICAPWorker("V6",True,                           clocked_by p125Clk , reset_by(vWci[0].mReset_n));
   //FMC150Ifc        fmc150 <- mkFMC150(True,sys0_clk,sys0_rst,flp_clk,flp_rst,  clocked_by p125Clk , reset_by(vWci[0].mReset_n));
   FMC150Ifc        fmc150 <- mkFMC150(True,                  flp_clk,flp_rst,  clocked_by p125Clk , reset_by(vWci[0].mReset_n));
   FlashWorkerIfc   flash0 <- mkFlashWorker(True,                               clocked_by p125Clk , reset_by(vWci[1].mReset_n));

bsv/top/FTop_n210.bsv

@@ -3,21 +3,19 @@
 
 // Application Imports...
 import ClockN210         ::*;
+import ICAPWorker        ::*;
 import LedN210           ::*;
 import Config            ::*;
 import OCCP              ::*;
-
-//import CPDefs            ::*;
-//import CTop              ::*;
-//import FlashWorker       ::*;
-
+import OCWip             ::*;
 import MDIO              ::*;
 import GMAC              ::*;
 import GbeLite           ::*;
 
+//import CPDefs            ::*;
+//import CTop              ::*;
+//import FlashWorker       ::*;
 //import GbeWorker         ::*;
-//import ICAPWorker        ::*;
-//import OCWip             ::*;
 //import SPICore32         ::*;
 //import SPICore5          ::*;
 //import TimeService       ::*;
@@ -83,6 +81,40 @@ module mkFTop_n210#(Clock sys0_clkp, Clock sys0_clkn,  // 100 MHz Board XO Refer
   OCCPIfc#(Nwcit)  cp         <- mkOCCP(?, sys2_clk, sys2_rst, clocked_by sys0_clk, reset_by sys0_rst);
   mkConnection(gbe0.cpClient, cp.server);
 
+  Vector#(Nwcit, WciEM) vWci = cp.wci_Vm;
+
+  WciSlaveNullIfc#(32) tieOff0  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff1  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff2  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff3  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff4  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff5  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff6  <- mkWciSlaveNull;
+  ICAPWorkerIfc    icap   <- mkICAPWorker("S3A", True, clocked_by sys0_clk, reset_by(vWci[7].mReset_n));
+  WciSlaveNullIfc#(32) tieOff8  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff9  <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff10 <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff11 <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff12 <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff13 <- mkWciSlaveNull;
+  WciSlaveNullIfc#(32) tieOff14 <- mkWciSlaveNull;
+
+  mkConnection(vWci[0],  tieOff0.slv); 
+  mkConnection(vWci[1],  tieOff1.slv); 
+  mkConnection(vWci[2],  tieOff2.slv); 
+  mkConnection(vWci[3],  tieOff3.slv); 
+  mkConnection(vWci[4],  tieOff4.slv); 
+  mkConnection(vWci[5],  tieOff5.slv); 
+  mkConnection(vWci[6],  tieOff6.slv); 
+  mkConnection(vWci[7],  icap.wciS0); 
+  mkConnection(vWci[8],  tieOff8.slv); 
+  mkConnection(vWci[9],  tieOff9.slv); 
+  mkConnection(vWci[10], tieOff10.slv); 
+  mkConnection(vWci[11], tieOff11.slv); 
+  mkConnection(vWci[12], tieOff12.slv); 
+  mkConnection(vWci[13], tieOff13.slv); 
+  mkConnection(vWci[14], tieOff14.slv); 
+
   method    Bit#(5)    led    = ledLogic.led;
   method    Bit#(32)   debug  = {16'h5555, 16'h0000};
   interface Clock      rxclkBnd   = gbe0.rxclkBnd;

bsv/wrk/ICAPWorker.bsv

@@ -1,5 +1,5 @@
 // ICAPWorker.bsv - A dedvice worker for communicating with the ICAP
-// Copyright (c) 2010 Atomic Rules LLC - ALL RIGHTS RESERVED
+// Copyright (c) 2010,2012 Atomic Rules LLC - ALL RIGHTS RESERVED
 
 import Accum::*;
 import ICAP::*;
@@ -25,7 +25,7 @@ interface ICAPWorkerIfc;
 endinterface 
 
 (* synthesize, default_clock_osc="wciS0_Clk", default_reset="wciS0_MReset_n" *)
-module mkICAPWorker#(parameter Bool isV6ICAP, parameter Bool hasDebugLogic) (ICAPWorkerIfc);
+module mkICAPWorker#(parameter String icapPrim, parameter Bool hasDebugLogic) (ICAPWorkerIfc);
 
   WciESlaveIfc                wci         <- mkWciESlave;
   Reg#(Bit#(32))              icapCtrl    <- mkReg(0);
@@ -35,7 +35,7 @@ module mkICAPWorker#(parameter Bool isV6ICAP, parameter Bool hasDebugLogic) (ICA
   ClockDividerIfc             cd          <- mkClockDivider(2);  // 125MHz/2 = 62.5 MHz
   Reset                       fastReset   <- exposeCurrentReset;
   Reset                       slowReset   <- mkAsyncResetFromCR(2, cd.slowClock);
-  ICAPIfc                     icap        <- mkICAP(clocked_by cd.slowClock, reset_by slowReset);
+  ICAPIfc                     icap        <- mkICAP(icapPrim, clocked_by cd.slowClock, reset_by slowReset);
   Reg#(Bool)                  cwe         <- mkSyncRegFromCC(False, cd.slowClock);
   Reg#(Bool)                  cre         <- mkSyncRegFromCC(False, cd.slowClock);
   Store#(UInt#(0),Bit#(32),0) cinS        <- mkRegStore(cd.fastClock, cd.slowClock);