make mkTLPSerializer a Verilog module

ShepardSiegel · Jun 21, 2013 · 652a840 · 652a840
1 parent f14046d
commit 652a840
Show file tree

Hide file tree

Showing 43 changed files with 721 additions and 598 deletions.
diff --git a/bsv/inf/TLPSerializer.bsv b/bsv/inf/TLPSerializer.bsv
@@ -28,6 +28,7 @@ typedef enum {Idle,RdPush,RdFinal} RdStage deriving (Bits, Eq);
 // For Reads:  Use the firstBE condition for the first DW, then make dwLength DW requests
 //             up until the last, where lastBE is used
 
+(* synthesize *)
 module mkTLPSerializer#(PciId pciDevice) (TLPSerializerIfc);
 
   FIFO#(PTW16)          inF                <- mkFIFO;   // inbound TLPs

diff --git a/bsv/utl/CompileTime.bsv b/bsv/utl/CompileTime.bsv
@@ -1 +1 @@
-Bit#(32) compileTime = 1359300735; // Verilog Sun Jan 27 10:32:15 EST 2013
+Bit#(32) compileTime = 1371848185; // Verilog Fri Jun 21 16:56:25 EDT 2013
diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:15 EST 2013
+// On Fri Jun 21 16:57:44 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:17 EST 2013
+// On Fri Jun 21 16:57:48 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:16 EST 2013
+// On Fri Jun 21 16:57:46 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:16 EST 2013
+// On Fri Jun 21 16:57:47 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkCTop16B.v b/rtl/mkCTop16B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:35:42 EST 2013
+// On Fri Jun 21 17:01:14 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkDramServer_v6.v b/rtl/mkDramServer_v6.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:32:52 EST 2013
+// On Fri Jun 21 16:57:13 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkFMC150.v b/rtl/mkFMC150.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:02 EST 2013
+// On Fri Jun 21 16:57:27 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkFTop_ml605.v b/rtl/mkFTop_ml605.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:35:46 EST 2013
+// On Fri Jun 21 17:01:19 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkFlashController2416.v b/rtl/mkFlashController2416.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:32:37 EST 2013
+// On Fri Jun 21 16:56:54 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkFlashWorker.v b/rtl/mkFlashWorker.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:32:57 EST 2013
+// On Fri Jun 21 16:57:20 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkGMAC.v b/rtl/mkGMAC.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:32:33 EST 2013
+// On Fri Jun 21 16:56:48 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkGbeWorker.v b/rtl/mkGbeWorker.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:07 EST 2013
+// On Fri Jun 21 16:57:33 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkICAPWorker.v b/rtl/mkICAPWorker.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:32:59 EST 2013
+// On Fri Jun 21 16:57:23 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkMemiTestWorker.v b/rtl/mkMemiTestWorker.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:19 EST 2013
+// On Fri Jun 21 16:57:50 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkOCApp16B.v b/rtl/mkOCApp16B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:33:30 EST 2013
+// On Fri Jun 21 16:58:05 EDT 2013
 //
 //
 // Ports:

diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:35:08 EST 2013
+// On Fri Jun 21 17:00:25 EDT 2013
 //
 //
 // Ports:
@@ -24330,7 +24330,7 @@ module mkOCCP(pciDevice,
 	      32'h00000001;
       8'h0C:
 	  IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 =
-	      32'd1359300735;
+	      32'd1371848185;
       8'h10:
 	  IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 =
 	      { 17'd0, x__h104311 };

diff --git a/rtl/mkOCDP16B.v b/rtl/mkOCDP16B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Sun Jan 27 10:35:33 EST 2013
+// On Fri Jun 21 17:01:01 EDT 2013
 //
 //
 // Ports:
Original file line number	Diff line number	Diff line change
		@@ -1 +1 @@
		Bit#(32) compileTime = 1359300735; // Verilog Sun Jan 27 10:32:15 EST 2013
		Bit#(32) compileTime = 1371848185; // Verilog Fri Jun 21 16:56:25 EDT 2013