update MemiTestWorker to support emmission of character to AXBLUART

ShepardSiegel · Feb 4, 2014 · 73f2ebf · 73f2ebf
1 parent fd35937
commit 73f2ebf
Show file tree

Hide file tree

Showing 13 changed files with 40,837 additions and 252 deletions.
diff --git a/bsv/utl/CompileTime.bsv b/bsv/utl/CompileTime.bsv
@@ -1 +1 @@
-Bit#(32) compileTime = 1391459380; // Verilog Mon Feb 3 15:29:40 EST 2014
+Bit#(32) compileTime = 1391543027; // Verilog Tue Feb 4 14:43:47 EST 2014
diff --git a/bsv/wrk/MemiTestWorker.bsv b/bsv/wrk/MemiTestWorker.bsv
@@ -46,6 +46,7 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc);
   Reg#(Bool)                     isTesting         <- mkReg(False);
   Reg#(Bool)                     isWriter          <- mkReg(True);
   Reg#(Bool)                     isReader          <- mkReg(False);
+  Reg#(Bool)                     isCharPush        <- mkReg(False);
   Reg#(UInt#(32))                hwordAddr         <- mkReg(0);
   Reg#(UInt#(32))                unrollCnt         <- mkReg(0);
   Reg#(UInt#(32))                respCnt           <- mkReg(0);
@@ -67,12 +68,13 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc);
   rule free_inc; freeCnt <= freeCnt + 1; endrule
 
   Bool haltOnError = unpack(tstCtrl[0]);
+  Bool charPerLoop = unpack(tstCtrl[1]);  // set to cause write to BLUART on loop
 
   function Bit#(36) hwordAsBytes(UInt#(32) hwAddr);
     return ( {pack(hwordAddr), 4'h0} );  // 4b up-shifted to convert hword to Bytes
   endfunction
 
-  rule write_req (wci.isOperating && isTesting && isWriter && !isReader);
+  rule write_req (wci.isOperating && isTesting && isWriter && !isReader && !isCharPush);
     let d <- wgen.stream.get;
     wmemi.req(True, hwordAsBytes(hwordAddr), 1);         // Write Request 
     wmemi.dh(d, '1, True);                               // Write 16B Datahandshake
@@ -98,6 +100,7 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc);
       testCycleCount <= testCycleCount + 1;
       wtCycStart <= freeCnt;
       rdDuration <= freeCnt - rdCycStart;
+      isCharPush <= charPerLoop;
     end
   endrule
 
@@ -111,7 +114,13 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc);
     end
     wmemiRdResp <= wmemiRdResp + 1;
   endrule
-
+
+  rule char_push (wci.isOperating && isTesting && isWriter && !isReader && isCharPush);
+    wmemi.req(True, 36'h08000002C, 1);                         // Write Request - set bit 31 to write AXI; 2C is TX
+    wmemi.dh(128'h0000000000000000000000000000002B, '1, True); // Write 16B Datahandshake 2B is ASCII '+'
+    isCharPush <= False;
+  endrule
+
 
 // WCI...
 Bit#(32) testStatus = {31'h0, pack(isReader)};

diff --git a/logs/ml605-20140204_1516/fpgaTop-ml605.srp b/logs/ml605-20140204_1516/fpgaTop-ml605.srp
diff --git a/logs/ml605-20140204_1516/fpgaTop.bld b/logs/ml605-20140204_1516/fpgaTop.bld
diff --git a/logs/ml605-20140204_1516/fpgaTop.par b/logs/ml605-20140204_1516/fpgaTop.par
diff --git a/logs/ml605-20140204_1516/fpgaTop.twr b/logs/ml605-20140204_1516/fpgaTop.twr
diff --git a/logs/ml605-20140204_1516/fpgaTop_map.mrp b/logs/ml605-20140204_1516/fpgaTop_map.mrp
diff --git a/rtl/mkCTop16B.v b/rtl/mkCTop16B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Mon Feb  3 15:31:29 EST 2014
+// On Tue Feb  4 14:45:38 EST 2014
 //
 //
 // Ports:

diff --git a/rtl/mkFTop_ml605.v b/rtl/mkFTop_ml605.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
 //
-// On Mon Feb  3 15:31:34 EST 2014
+// On Tue Feb  4 14:45:44 EST 2014
 //
 //
 // Ports:
Original file line number	Diff line number	Diff line change
		@@ -1 +1 @@
		Bit#(32) compileTime = 1391459380; // Verilog Mon Feb 3 15:29:40 EST 2014
		Bit#(32) compileTime = 1391543027; // Verilog Tue Feb 4 14:43:47 EST 2014