core960 nop push

ShepardSiegel · Sep 24, 2012 · c865f5e · c865f5e
1 parent 599a6e5
commit c865f5e
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Showing 33 changed files with 2,454 additions and 2,423 deletions.
diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
 //
-// On Fri Sep 21 13:44:59 EDT 2012
+// On Mon Sep 24 13:38:19 EDT 2012
 //
 //
 // Ports:

diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
 //
-// On Fri Sep 21 13:45:02 EDT 2012
+// On Mon Sep 24 13:38:20 EDT 2012
 //
 //
 // Ports:

diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
 //
-// On Fri Sep 21 13:45:00 EDT 2012
+// On Mon Sep 24 13:38:17 EDT 2012
 //
 //
 // Ports:
@@ -521,7 +521,7 @@ module mkBiasWorker4B(wciS0_Clk,
   reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
   wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
 		MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
-		MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
+		MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
   wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
 		MUX_wci_wslv_respF_q_1$write_1__VAL_1,
 		MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
@@ -537,8 +537,8 @@ module mkBiasWorker4B(wciS0_Clk,
        MUX_wci_wslv_illegalEdge$write_1__VAL_1,
        MUX_wci_wslv_respF_q_0$write_1__SEL_2,
        MUX_wci_wslv_respF_q_1$write_1__SEL_2,
-       MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
-       MUX_wsiM_reqFifo_q_1$write_1__SEL_2,
+       MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
+       MUX_wsiM_reqFifo_q_1$write_1__SEL_1,
        MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3;
 
   // remaining internal signals
@@ -751,9 +751,9 @@ module mkBiasWorker4B(wciS0_Clk,
   assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 =
 	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
 	     wci_wslv_respF_c_r == 2'd1 ;
-  assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
+  assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 =
 	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
-  assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
+  assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 =
 	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
   assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
 	     wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
@@ -797,16 +797,16 @@ module mkBiasWorker4B(wciS0_Clk,
   assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
   assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
   assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
-	     (wsiM_reqFifo_c_r == 2'd1) ?
-	       MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
-	       wsiM_reqFifo_q_1 ;
-  assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
 	     { wsiS_reqFifo$D_OUT[60:44],
 	       x_data__h10151,
 	       wsiS_reqFifo$D_OUT[11:0] } ;
-  assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
+  assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
+	     (wsiM_reqFifo_c_r == 2'd1) ?
+	       MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
+	       wsiM_reqFifo_q_1 ;
+  assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 =
 	     (wsiM_reqFifo_c_r == 2'd2) ?
-	       MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
+	       MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
 	       61'h00000AAAAAAAAA00 ;
 
   // inlined wires
@@ -855,7 +855,7 @@ module mkBiasWorker4B(wciS0_Clk,
   assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
   assign wsiS_sThreadBusy_dw$whas =
 	     wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
-  assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ;
+  assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ;
   assign wsiM_reqFifo_x_wire$whas =
 	     MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ;
   assign wsiM_operateD_1$wget = 1'd1 ;
@@ -1108,16 +1108,16 @@ module mkBiasWorker4B(wciS0_Clk,
 	     WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
 
   // register wsiM_reqFifo_q_0
-  always@(WILL_FIRE_RL_wsiM_reqFifo_both or
+  always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or
 	  MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
-	  MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
+	  WILL_FIRE_RL_wsiM_reqFifo_both or
 	  MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
 	  WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
   begin
     case (1'b1) // synopsys parallel_case
-      WILL_FIRE_RL_wsiM_reqFifo_both:
+      MUX_wsiM_reqFifo_q_0$write_1__SEL_1:
 	  wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
-      MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
+      WILL_FIRE_RL_wsiM_reqFifo_both:
 	  wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
       WILL_FIRE_RL_wsiM_reqFifo_decCtr:
 	  wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
@@ -1126,31 +1126,31 @@ module mkBiasWorker4B(wciS0_Clk,
     endcase
   end
   assign wsiM_reqFifo_q_0$EN =
-	     WILL_FIRE_RL_wsiM_reqFifo_both ||
 	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
+	     WILL_FIRE_RL_wsiM_reqFifo_both ||
 	     WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
 
   // register wsiM_reqFifo_q_1
-  always@(WILL_FIRE_RL_wsiM_reqFifo_both or
-	  MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
-	  MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
-	  MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
+  always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or
+	  MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
+	  WILL_FIRE_RL_wsiM_reqFifo_both or
+	  MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or
 	  WILL_FIRE_RL_wsiM_reqFifo_decCtr)
   begin
     case (1'b1) // synopsys parallel_case
+      MUX_wsiM_reqFifo_q_1$write_1__SEL_1:
+	  wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
       WILL_FIRE_RL_wsiM_reqFifo_both:
-	  wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
-      MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
-	  wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
+	  wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
       WILL_FIRE_RL_wsiM_reqFifo_decCtr:
 	  wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
       default: wsiM_reqFifo_q_1$D_IN =
 		   61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
     endcase
   end
   assign wsiM_reqFifo_q_1$EN =
-	     WILL_FIRE_RL_wsiM_reqFifo_both ||
 	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
+	     WILL_FIRE_RL_wsiM_reqFifo_both ||
 	     WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
 
   // register wsiM_sThreadBusy_d

diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v
@@ -1,7 +1,7 @@
 //
 // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
 //
-// On Fri Sep 21 13:45:01 EDT 2012
+// On Mon Sep 24 13:38:18 EDT 2012
 //
 //
 // Ports: