Project 2 peer review submission #10
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Thank you for your pull request! 👋 |
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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"opt_in labels issue.. not sure yet what is wrong but still debugging" good! |
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I currently have 15 verification errors due to:
waveguide at the edge of chip (waived)
waveguide overlapping due to directional coupler input pitch (waived)
opt_in labels issue.. not sure yet what is wrong but still debugging