Peer Review for Project 2

[bgosal02]

Ignore the "overlapping components" verification error.

[github-actions]

Thank you for your pull request! 👋

[github-actions]

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

[lukasc-ubc]

• connect the input to the on-chip laser, at (0,10)
• the ∆L looks too small

[github-actions]

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

[github-actions]

Thank you for your pull request! 👋

[github-actions]

Thank you for your pull request! 👋