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Add files via upload #28

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julianaangel
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Chip 2 first draft

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github-actions bot commented Feb 6, 2025

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

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github-actions bot commented Feb 6, 2025

Thank you for your pull request! 👋

@lukasc-ubc
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  • missing opt_in label
  • ∆L looks too small perhaps, for a 25 GHz FSR

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2 participants