Added Initial Chip2 Draft #34
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Bounding box is said to be 605.01um x 410um and its due to the unterminated pin of the waveguide at (0um, 10um). The pin is centered at the layout border but because it is a rectangle, half of it protrudes out of the 605um x 410um box
