Add new file #4
Add new file #4
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This layout contains a set of loopbacks to characterize the GC_SiN_TE_1550_8degOxide_BB GC. However, this component has a pin issue. I believe this is the source of all the DRC issues with my layout.
Running functional verification ("V") on a layout with a single GC_SiN_TE_1550_8degOxide_BB component produces the following error:
Invalid Pin [TOP]
Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
polygon: (9.115,0.575;9.115,0.585;9.125,0.585;9.125,0.575)
The components with the pin problem is: GC_SiN_TE_1550_8degOxide_BB
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"Merge branch 'SiEPIC:main' into main" This commit was an accident. Not sure if it does anything. Please reject my pull request if it is a problem. |
moving SiN to Layer 4/0
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit. You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Applied Nanotools asked us to change to Layer 4/0. I have updated the SiEPIC EBeam PDK. I updated your design accordingly. |
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thank you |
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I was not able to update the SiEPIC EBeam PDK using the KLayout package manager. It didn't give me the option to download the latest version (v0.4.20). However, I updated the PDK manually by cloning the repo and copying the files to my KLayout directory. |
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