Version 1 of my silicon photonics circuit #36
Conversation
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit. You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Error: Cell bounding box / extent (643.82, 410.0) is larger than the maximum size of 605.0 X 410.0 microns |
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Also three Verification errors. can you please fix? |
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Terminate the unused ports and update the pull request. |
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit. You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Thank you for your pull request! Staff will review your submission, and if it passes all checks, it will be merged. After merging, you may check the merged file. 👋 |
Fixing verification errors
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit. You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Thank you for your pull request! Staff will review your submission, and if it passes all checks, it will be merged. After merging, you may check the merged file. 👋 |
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit. You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Thank you for your pull request! Staff will review your submission, and if it passes all checks, it will be merged. After merging, you may check the merged file. 👋 |
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). Please note that we have added a new rule (on May 2, 2024) to SiEPIC-Tools and the EBeam PDK, so please make sure your tools are running the latest version. The rule is: The grating coupler spacing (pitch) must be at least 60.0 microns. This is to help avoid the probe station from accidentally aligning to an adjacent circuit. You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Thank you for your pull request! Staff will review your submission, and if it passes all checks, it will be merged. After merging, you may check the merged file. 👋 |
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Hello, I have made the fixes to my branch. It should be error free now |
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