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Initial Design Draft for the Silicon photonics design course performed by Javad Babaki #48

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@J-babaki J-babaki commented Feb 2, 2025

In this design draft, I have not deleted the laser sources and detectors on the layout.
tnx

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github-actions bot commented Feb 2, 2025

Thank you for your pull request! 👋

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github-actions bot commented Feb 2, 2025

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

@J-babaki J-babaki changed the title Initial Design Draft for Silicon photonics design course by Javad Babaki Initial Design Draft for the Silicon photonics design course performed by Javad Babaki Feb 2, 2025
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J-babaki commented Feb 2, 2025

this error actually comes from the size of Floor Plan. while it shows in Klayout is as exactly same as (605*410), here it says that the y-axis is larger than 410 um. So I am going to resize the BOX size and resend it again.

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github-actions bot commented Feb 2, 2025

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

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github-actions bot commented Feb 2, 2025

Thank you for your pull request! 👋

@J-babaki J-babaki closed this Feb 2, 2025
@J-babaki J-babaki reopened this Feb 2, 2025
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github-actions bot commented Feb 2, 2025

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

Copy link

github-actions bot commented Feb 2, 2025

Thank you for your pull request! 👋

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github-actions bot commented Feb 2, 2025

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

Copy link

github-actions bot commented Feb 2, 2025

Thank you for your pull request! 👋

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