-
Notifications
You must be signed in to change notification settings - Fork 54
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Initial Design Draft for the Silicon photonics design course performed by Javad Babaki #48
base: main
Are you sure you want to change the base?
Conversation
Thank you for your pull request! 👋 |
Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
this error actually comes from the size of Floor Plan. while it shows in Klayout is as exactly same as (605*410), here it says that the y-axis is larger than 410 um. So I am going to resize the BOX size and resend it again. |
Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
Thank you for your pull request! 👋 |
Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
Thank you for your pull request! 👋 |
Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
Thank you for your pull request! 👋 |
In this design draft, I have not deleted the laser sources and detectors on the layout.
tnx