Initial commit

.devcontainer/Dockerfile

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+ARG VARIANT=ubuntu-22.04
+FROM mcr.microsoft.com/vscode/devcontainers/base:${VARIANT}
+
+ENV DEBIAN_FRONTEND=noninteractive
+ENV PDK_ROOT=/home/vscode/ttsetup/pdk
+ENV PDK=sky130A
+
+RUN apt update
+RUN apt install -y iverilog gtkwave python3 python3-pip python3-venv python3-tk python-is-python3 libcairo2 verilator libpng-dev libqhull-dev
+
+# Clone tt-support-tools
+RUN mkdir -p /ttsetup
+RUN git clone -b tt10 https://github.com/TinyTapeout/tt-support-tools /ttsetup/tt-support-tools
+
+COPY test/requirements.txt /ttsetup/test_requirements.txt
+COPY .devcontainer/copy_tt_support_tools.sh /ttsetup
+
+RUN pip3 install -r /ttsetup/test_requirements.txt -r /ttsetup/tt-support-tools/requirements.txt
+
+# Install verible (for formatting)
+RUN umask 022 && \
+    curl -L https://github.com/chipsalliance/verible/releases/download/v0.0-3795-gf4d72375/verible-v0.0-3795-gf4d72375-linux-static-x86_64.tar.gz | \
+    tar zxf - -C /usr/local --strip-components=1 && \
+    chmod 755 /usr/local/bin
+
+# Install openlane
+RUN pip3 install openlane==2.1.5

.devcontainer/copy_tt_support_tools.sh

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+#! /bin/sh
+
+if [ ! -L tt ]; then
+    cp -R /ttsetup/tt-support-tools tt
+    cd tt && git pull && cd ..
+fi

.devcontainer/devcontainer.json

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+// For format details, see https://aka.ms/devcontainer.json. For config options, see the README at:
+// https://github.com/microsoft/vscode-dev-containers/tree/v0.183.0/containers/ubuntu
+{
+  "name": "Tiny Tapeout Dev Container",
+  "build": {
+    "dockerfile": "Dockerfile",
+    "context": ".."
+  },
+  "runArgs": [
+    "--memory=10GB"
+  ],
+  "customizations": {
+    "vscode": {
+      "settings": {
+        "terminal.integrated.defaultProfile.linux": "bash"
+      },
+      "extensions": ["mshr-h.veriloghdl", "surfer-project.surfer"]
+    }
+  },
+  "features": {
+    "ghcr.io/devcontainers/features/docker-in-docker:2": {
+      "moby": true,
+      "azureDnsAutoDetection": true,
+      "version": "latest",
+      "dockerDashComposeVersion": "none"
+    }
+  },
+  "postStartCommand": "/ttsetup/copy_tt_support_tools.sh"
+}

.github/workflows/docs.yaml

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+name: docs
+
+on:
+  push:
+  workflow_dispatch:
+
+jobs:
+  docs:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Checkout repo
+        uses: actions/checkout@v4
+        with:
+          submodules: recursive
+
+      # Build Verilog if necessary from, e.g. TL-Verilog (to satisfy Verilog existence check).
+      - name: Build Verilog
+        run: |
+          cd test
+          make verilog
+
+      - name: Build docs
+        uses: TinyTapeout/tt-gds-action/docs@tt10

.github/workflows/fpga.yaml

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+name: fpga
+
+on:
+  push:
+    # Comment out (or remove) the following line to run the FPGA workflow on every push:
+    #branches: none
+  workflow_dispatch:
+
+jobs:
+  fpga:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: checkout repo
+        uses: actions/checkout@v4
+        with:
+          submodules: recursive
+      # Build Verilog if necessary from, e.g. TL-Verilog.
+      - name: Build Verilog
+        run: |
+          cd test
+          make verilog
+
+      - name: FPGA bitstream for TT ASIC Sim (ICE40UP5K)
+        uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt10

.github/workflows/gds.yaml

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+name: gds
+
+on:
+  push:
+  workflow_dispatch:
+
+jobs:
+  gds:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: checkout repo
+        uses: actions/checkout@v4
+        with:
+          submodules: recursive
+
+      # Build Verilog if necessary from, e.g. TL-Verilog.
+      - name: Build Verilog
+        run: |
+          cd test
+          make verilog
+
+      - name: Build GDS
+        uses: TinyTapeout/tt-gds-action@tt10
+        with:
+          flow: openlane2
+
+  precheck:
+    needs: gds
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Run Tiny Tapeout Precheck
+        uses: TinyTapeout/tt-gds-action/precheck@tt10
+
+  gl_test:
+    needs: gds
+    runs-on: ubuntu-24.04
+    steps:
+      - name: checkout repo
+        uses: actions/checkout@v4
+        with:
+          submodules: recursive
+
+      - name: GL test
+        uses: TinyTapeout/tt-gds-action/gl_test@tt10
+
+  viewer:
+    needs: gds
+    runs-on: ubuntu-24.04
+    permissions:
+      pages: write      # to deploy to Pages
+      id-token: write   # to verify the deployment originates from an appropriate source
+    steps:
+      - uses: TinyTapeout/tt-gds-action/viewer@tt10

.github/workflows/test.yaml

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+name: test
+on: [push, workflow_dispatch]
+jobs:
+  test:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Checkout repo
+        uses: actions/checkout@v4
+        with:
+          submodules: recursive
+
+      - name: Install iverilog
+        shell: bash
+        run: sudo apt-get update && sudo apt-get install -y iverilog
+
+      # Set Python up and install cocotb
+      - name: Setup python
+        uses: actions/setup-python@v5
+        with:
+          python-version: '3.11'
+
+      - name: Install Python packages
+        shell: bash
+        run: pip install -r test/requirements.txt
+
+      - name: Run tests
+        run: |
+          cd test
+          make clean
+          make
+          # make will return success even if the test fails, so check for failure in the results.xml
+          ! grep failure results.xml
+
+      - name: Test Summary
+        uses: test-summary/[email protected]
+        with:
+          paths: "test/results.xml"
+        if: always()
+
+      - name: upload vcd
+        if: success() || failure()
+        uses: actions/upload-artifact@v4
+        with:
+          name: test-vcd
+          path: |
+            test/tb.vcd
+            test/results.xml

.gitignore

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+.DS_Store
+.idea
+.vscode
+*.vcd
+runs
+tt_submission
+src/user_config.json
+src/config_merged.json
+test/sim_build
+test/__pycache__/
+test/results.xml
+test/gate_level_netlist.v