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Removing compiler warnings and errors
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akashlevy committed Nov 23, 2024
1 parent 70f7778 commit c3d6821
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Showing 3 changed files with 9 additions and 1 deletion.
2 changes: 2 additions & 0 deletions frontends/verific/decorate_loops.h
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,8 @@
*
*/
#ifdef VERIFIC_LINEFILE_INCLUDES_LOOPS
#include <stack>

/*
This Visitor decorates the AST with a loop ID attribute for all outer for loops.
All AST nodes contained within the subtree of an outer for-loop
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6 changes: 6 additions & 0 deletions frontends/verific/verific.cc
Original file line number Diff line number Diff line change
Expand Up @@ -2881,6 +2881,8 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
}
continue;
}
#else
(void) top; // silience warnings
#endif
log_error("Can't find module/unit '%s'.\n", name);
}
Expand Down Expand Up @@ -3794,7 +3796,9 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F" || args[argidx] == "-FF"))
{
unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
bool is_formal = false;
#endif
const char* filename = nullptr;

#ifndef SILIMATE_VERIFIC_EXTENSIONS
Expand All @@ -3817,7 +3821,9 @@ struct VerificPass : public Pass {
continue;
} else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") {
verilog_mode = veri_file::SYSTEM_VERILOG;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (args[argidx] == "-formal") is_formal = true;
#endif
continue;
} else if (args[argidx].compare(0, 1, "-") == 0) {
cmd_error(args, argidx, "unknown option");
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2 changes: 1 addition & 1 deletion verific

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