Exposed write mask on default iBus

SpinalHDL · Jun 4, 2024 · 1175f19 · 1175f19
1 parent 457ae5c
commit 1175f19
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -16,6 +16,7 @@ import scala.collection.mutable.ArrayBuffer
 
 case class DBusSimpleCmd() extends Bundle{
   val wr = Bool
+  val mask = Bits(4 bit)
   val address = UInt(32 bits)
   val data = Bits(32 bit)
   val size = UInt(2 bit)
@@ -441,6 +442,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
 
       //formal
       val formalMask = dBus.genMask(dBus.cmd)
+      dBus.cmd.mask := formalMask
 
       insert(FORMAL_MEM_ADDR) := dBus.cmd.address & U"xFFFFFFFC"
       insert(FORMAL_MEM_WMASK) := (dBus.cmd.valid &&  dBus.cmd.wr) ? formalMask | B"0000"