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Merge remote-tracking branch 'origin/dev' into dev
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@Dolu1990
Dolu1990 committed Mar 5, 2024
2 parents 9834bba + 3799ebf commit 68c0db3
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Showing 4 changed files with 66 additions and 39 deletions.
8 changes: 4 additions & 4 deletions build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,14 @@ lazy val root = (project in file(".")).
settings(
inThisBuild(List(
organization := "com.github.spinalhdl",
scalaVersion := "2.11.12",
scalaVersion := "2.12.18",
version := "2.0.0"
)),
scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/../SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}",
scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/../SpinalHDL/idslplugin/target/scala-2.12/spinalhdl-idsl-plugin_2.12-$spinalVersion.jar")}",
scalacOptions += s"-Xplugin-require:idsl-plugin",
libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.2.5",
"org.yaml" % "snakeyaml" % "1.8"
"org.yaml" % "snakeyaml" % "1.8",
"org.scalatest" %% "scalatest" % "3.2.14" % "test"
),
name := "VexRiscv"
).dependsOn(spinalHdlIdslPlugin, spinalHdlSim,spinalHdlCore,spinalHdlLib)
Expand Down
4 changes: 0 additions & 4 deletions src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -120,10 +120,6 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
case _ =>
}

config.plugins += new IBusDBusCachedTightlyCoupledRam(
mapping = SizeMapping(0x20000000, 0x1000)
)

val cpu = new VexRiscv(config)
def doExport(value : => Any, postfix : String) = {
sexport(Handle(value).setCompositeName(VexRiscvBmbGenerator.this, postfix))
Expand Down
38 changes: 25 additions & 13 deletions src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ import spinal.lib.com.jtag.xilinx.Bscane2BmbMasterGenerator
import spinal.lib.generator._
import spinal.core.fiber._
import spinal.idslplugin.PostInitCallback
import spinal.lib.cpu.riscv.debug.{DebugModule, DebugModuleCpuConfig, DebugModuleParameter, DebugTransportModuleParameter, DebugTransportModuleTunneled}
import spinal.lib.cpu.riscv.debug.{DebugModule, DebugModuleCpuConfig, DebugModuleParameter, DebugTransportModuleJtagTap, DebugTransportModuleJtagTapWithTunnel, DebugTransportModuleParameter, DebugTransportModuleTunneled}
import spinal.lib.misc.plic.PlicMapping
import spinal.lib.system.debugger.SystemDebuggerConfig
import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
Expand All @@ -33,7 +33,8 @@ case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig],
outOfOrderDecoder : Boolean = true,
fpu : Boolean = false,
privilegedDebug : Boolean = false,
hardwareBreakpoints : Int = 0)
hardwareBreakpoints : Int = 0,
jtagTap : Boolean = false)

class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with PostInitCallback{
val cpuCount = p.cpuConfigs.size
Expand Down Expand Up @@ -100,12 +101,11 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
}

val privilegedDebug = p.privilegedDebug generate new Area{
val jtagCd = ClockDomain.external("jtag", withReset = false)

val systemReset = Handle(Bool())
systemCd.relaxedReset(systemReset, ResetSensitivity.HIGH)

val p = DebugTransportModuleParameter(
val dp = DebugTransportModuleParameter(
addressWidth = 7,
version = 1,
idle = 7
Expand All @@ -116,7 +116,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with

val dm = DebugModule(
DebugModuleParameter(
version = p.version + 1,
version = dp.version + 1,
harts = cpuCount,
progBufSize = 2,
datacount = XLEN / 32 + cores.exists(_.cpu.config.get.FLEN == 64).toInt,
Expand All @@ -136,14 +136,26 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with

val clintStop = (cores.map(e => e.cpu.logic.cpu.service(classOf[CsrPlugin]).stoptime).andR)

val tunnel = DebugTransportModuleTunneled(
p = p,
jtagCd = jtagCd,
debugCd = ClockDomain.current
)
dm.io.ctrl <> tunnel.io.bus
val noTap = !p.jtagTap generate new Area {
val jtagCd = ClockDomain.external("jtag", withReset = false)

val tunnel = DebugTransportModuleTunneled(
p = dp,
jtagCd = jtagCd,
debugCd = ClockDomain.current
)
dm.io.ctrl <> tunnel.io.bus
val debugPort = Handle(tunnel.io.instruction.toIo).setName("debugPort")
}

val debugPort = Handle(tunnel.io.instruction.toIo).setName("debugPort")
val withTap = p.jtagTap generate new Area {
val tunnel = DebugTransportModuleJtagTapWithTunnel(
p = dp,
debugCd = ClockDomain.current
)
dm.io.ctrl <> tunnel.io.bus
val debugPort = Handle(tunnel.io.jtag.toIo).setName("debugPort")
}
})
}
}
Expand Down Expand Up @@ -262,7 +274,7 @@ object VexRiscvSmpClusterGen {
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
assert(!(withDouble && !withFloat))

val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "s" else ""}")
val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "su" else ""}")
val csrConfig = if(withSupervisor){
var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug)
if(csrFull){
Expand Down
55 changes: 37 additions & 18 deletions src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -107,13 +107,15 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
object VexRiscvLitexSmpClusterCmdGen extends App {
Handle.loadHandleAsync = true
var cpuCount = 1
var resetVector = 0l
var iBusWidth = 64
var dBusWidth = 64
var iCacheSize = 8192
var dCacheSize = 8192
var iCacheWays = 2
var dCacheWays = 2
var privilegedDebug = false
var jtagTap = false
var hardwareBreakpoints = 0
var liteDramWidth = 128
var coherentDma = false
Expand All @@ -133,13 +135,15 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
help("help").text("prints this usage text")
opt[Unit] ("coherent-dma") action { (v, c) => coherentDma = true }
opt[String]("cpu-count") action { (v, c) => cpuCount = v.toInt }
opt[String]("reset-vector") action { (v, c) => resetVector = v.toLong }
opt[String]("ibus-width") action { (v, c) => iBusWidth = v.toInt }
opt[String]("dbus-width") action { (v, c) => dBusWidth = v.toInt }
opt[String]("icache-size") action { (v, c) => iCacheSize = v.toInt }
opt[String]("dcache-size") action { (v, c) => dCacheSize = v.toInt }
opt[String]("icache-ways") action { (v, c) => iCacheWays = v.toInt }
opt[String]("dcache-ways") action { (v, c) => dCacheWays = v.toInt }
opt[Boolean]("privileged-debug") action { (v, c) => privilegedDebug = v }
opt[Boolean]("jtag-tap") action { (v, c) => jtagTap = v }
opt[Int] ("hardware-breakpoints") action { (v, c) => hardwareBreakpoints = v }
opt[String]("litedram-width") action { (v, c) => liteDramWidth = v.toInt }
opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v }
Expand All @@ -163,7 +167,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
val c = vexRiscvConfig(
hartId = hartId,
ioRange = address => address.msb,
resetVector = 0,
resetVector = resetVector,
iBusWidth = iBusWidth,
dBusWidth = dBusWidth,
iCacheSize = iCacheSize,
Expand Down Expand Up @@ -192,7 +196,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
fpu = fpu,
jtagHeaderIgnoreWidth = 0,
privilegedDebug = privilegedDebug,
hardwareBreakpoints = hardwareBreakpoints
hardwareBreakpoints = hardwareBreakpoints,
jtagTap = jtagTap
),
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
Expand Down Expand Up @@ -252,27 +257,29 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
////addAttribute("""mark_debug = "true"""")
object VexRiscvLitexSmpClusterOpenSbi extends App{
import spinal.core.sim._
Handle.loadHandleAsync = true

val simConfig = SimConfig
simConfig.withWave
simConfig.withFstWave
simConfig.allOptimisation

val cpuCount = 2
val cpuCount = 1

def parameter = VexRiscvLitexSmpClusterParameter(
cluster = VexRiscvSmpClusterParameter(
cpuConfigs = List.tabulate(cpuCount) { hartId =>
vexRiscvConfig(
hartId = hartId,
ioRange = address => address(31 downto 28) === 0xF,
resetVector = 0x80000000l
resetVector = 0x40f00000l,
rvc = true
)
},
withExclusiveAndInvalidation = true,
jtagHeaderIgnoreWidth = 0
),
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
liteDramMapping = SizeMapping(0x80000000l, 0x70000000l),
liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
coherentDma = false,
wishboneMemory = false,
cpuPerFpu = 4,
Expand Down Expand Up @@ -305,12 +312,24 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{

simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut =>
dut.body.debugCd.inputClockDomain.get.forkStimulus(10)
fork{
sleep(20)
dut.body.debugCd.inputClockDomain.clockToggle()
sleep(20)
dut.body.debugCd.inputClockDomain.clockToggle()
}

val ram = SparseMemory()
ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
val dist = "/media/data2/proj/upstream/nuttex/test1/dist"
// ram.write(0x80000000l, Seq(0xb7, 0x0f, 0x00, 0x40, 0xe7, 0x80, 0x0f,0x00).map(_.toByte).toArray) //Seq(0x80000fb7, 0x000f80e7)
ram.loadBin(0xC00000, dist + "/romfs.img")
ram.loadBin(0x0000000, dist + "/nuttx.bin")
ram.loadBin(0xf00000, dist + "/opensbi.bin")

// ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
// ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
// ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
// ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")


dut.body.iBridge.dram.simSlave(ram, dut.body.debugCd.inputClockDomain)
Expand All @@ -328,13 +347,13 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
}
}

fork{
while(true) {
disableSimWave()
sleep(100000 * 10)
enableSimWave()
sleep( 100 * 10)
}
}
// fork{
// while(true) {
// disableSimWave()
// sleep(100000 * 10)
// enableSimWave()
// sleep( 100 * 10)
// }
// }
}
}

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