VexRiscvBmbGenerator now export IBusDBusCachedTightlyCoupledRam

SpinalHDL · Jan 31, 2024 · 7723afc · 7723afc
1 parent 0347173
commit 7723afc
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Showing 2 changed files with 15 additions and 7 deletions.
diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
@@ -2,7 +2,7 @@ package vexriscv
 
 import spinal.core._
 import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbImplicitDebugDecoder, BmbInterconnectGenerator, BmbInvalidationParameter, BmbParameter}
-import spinal.lib.bus.misc.AddressMapping
+import spinal.lib.bus.misc.{AddressMapping, SizeMapping}
 import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
 import spinal.lib.generator._
 import spinal.lib.{sexport, slave}
@@ -120,6 +120,10 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
       case _ =>
     }
 
+    config.plugins += new IBusDBusCachedTightlyCoupledRam(
+      mapping = SizeMapping(0x20000000, 0x1000)
+    )
+
     val cpu = new VexRiscv(config)
     def doExport(value : => Any, postfix : String) = {
       sexport(Handle(value).setCompositeName(VexRiscvBmbGenerator.this, postfix))
@@ -142,6 +146,10 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
         doExport(plugin.config.cacheSize, "dcacheSize")
         doExport(plugin.config.bytePerLine, "bytesPerLine")
       }
+      case plugin : IBusDBusCachedTightlyCoupledRam => {
+        doExport(plugin.mapping.base, "coupledRamBase")
+        doExport(plugin.mapping.size, "coupledRamSize")
+      }
       case plugin: MmuPlugin => {
         doExport(true, "mmu")
       }

diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -651,12 +651,12 @@ class DBusCachedPlugin(val config : DataCacheConfig,
 }
 
 
-class IBusDBusCachedTightlyCoupledRam(mapping : SizeMapping,
-                                      withIBus : Boolean = true,
-                                      withDBus : Boolean = true,
-                                      ramAsBlackbox : Boolean = true,
-                                      hexInit :   String = null,
-                                      ramOffset : Long = -1) extends Plugin[VexRiscv]{
+class IBusDBusCachedTightlyCoupledRam(var mapping : SizeMapping,
+                                      var withIBus : Boolean = true,
+                                      var withDBus : Boolean = true,
+                                      var ramAsBlackbox : Boolean = true,
+                                      var hexInit :   String = null,
+                                      var ramOffset : Long = -1) extends Plugin[VexRiscv]{
   var dbus : TightlyCoupledDataBus = null
   var ibus : TightlyCoupledBus = null