Allow for WE/WEL in sticky/stickybit fields

src/peakrdl_regblock/field_logic/__init__.py

@@ -9,6 +9,7 @@
 from . import hw_write
 from . import hw_set_clr
 from . import hw_interrupts
+from . import hw_interrupts_with_write
 
 from ..utils import get_indexed_path
 from ..sv_int import SVInt
@@ -366,12 +367,19 @@ def init_conditionals(self) -> None:
 
         self.add_sw_conditional(sw_singlepulse.Singlepulse(self.exp), AssignmentPrecedence.SW_SINGLEPULSE)
 
+        self.add_hw_conditional(hw_interrupts_with_write.PosedgeStickybitWE(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.PosedgeStickybitWEL(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.NegedgeStickybitWE(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.NegedgeStickybitWEL(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.BothedgeStickybitWE(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.BothedgeStickybitWEL(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.StickyWE(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.StickyWEL(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.StickybitWE(self.exp), AssignmentPrecedence.HW_WRITE)
+        self.add_hw_conditional(hw_interrupts_with_write.StickybitWEL(self.exp), AssignmentPrecedence.HW_WRITE)
         self.add_hw_conditional(hw_interrupts.PosedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
         self.add_hw_conditional(hw_interrupts.NegedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
         self.add_hw_conditional(hw_interrupts.BothedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
-        self.add_hw_conditional(hw_interrupts.PosedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
-        self.add_hw_conditional(hw_interrupts.NegedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
-        self.add_hw_conditional(hw_interrupts.BothedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
         self.add_hw_conditional(hw_interrupts.Sticky(self.exp), AssignmentPrecedence.HW_WRITE)
         self.add_hw_conditional(hw_interrupts.Stickybit(self.exp), AssignmentPrecedence.HW_WRITE)
         self.add_hw_conditional(hw_write.WEWrite(self.exp), AssignmentPrecedence.HW_WRITE)

src/peakrdl_regblock/field_logic/hw_interrupts.py

@@ -132,66 +132,3 @@ def get_assignments(self, field: 'FieldNode') -> List[str]:
             f"next_c = {R} | ({Iq} ^ {I});",
             "load_next_c = '1;",
         ]
-
-class PosedgeNonsticky(NextStateConditional):
-    """
-    Positive edge non-stickybit
-    """
-    is_unconditional = True
-    comment = "posedge nonsticky"
-    def is_match(self, field: 'FieldNode') -> bool:
-        return (
-            field.is_hw_writable
-            and not field.get_property('stickybit')
-            and field.get_property('intr type') == InterruptType.posedge
-        )
-
-    def get_assignments(self, field: 'FieldNode') -> List[str]:
-        I = self.exp.hwif.get_input_identifier(field)
-        Iq = self.exp.field_logic.get_next_q_identifier(field)
-        return [
-            f"next_c = ~{Iq} & {I};",
-            "load_next_c = '1;",
-        ]
-
-class NegedgeNonsticky(NextStateConditional):
-    """
-    Negative edge non-stickybit
-    """
-    is_unconditional = True
-    comment = "negedge nonsticky"
-    def is_match(self, field: 'FieldNode') -> bool:
-        return (
-            field.is_hw_writable
-            and not field.get_property('stickybit')
-            and field.get_property('intr type') == InterruptType.negedge
-        )
-
-    def get_assignments(self, field: 'FieldNode') -> List[str]:
-        I = self.exp.hwif.get_input_identifier(field)
-        Iq = self.exp.field_logic.get_next_q_identifier(field)
-        return [
-            f"next_c = {Iq} & ~{I};",
-            "load_next_c = '1;",
-        ]
-
-class BothedgeNonsticky(NextStateConditional):
-    """
-    edge-sensitive non-stickybit
-    """
-    is_unconditional = True
-    comment = "bothedge nonsticky"
-    def is_match(self, field: 'FieldNode') -> bool:
-        return (
-            field.is_hw_writable
-            and not field.get_property('stickybit')
-            and field.get_property('intr type') == InterruptType.bothedge
-        )
-
-    def get_assignments(self, field: 'FieldNode') -> List[str]:
-        I = self.exp.hwif.get_input_identifier(field)
-        Iq = self.exp.field_logic.get_next_q_identifier(field)
-        return [
-            f"next_c = {Iq} ^ {I};",
-            "load_next_c = '1;",
-        ]

src/peakrdl_regblock/field_logic/hw_interrupts_with_write.py

@@ -0,0 +1,187 @@
+from typing import List, TYPE_CHECKING
+
+from .hw_interrupts import (
+    Sticky, Stickybit,
+    PosedgeStickybit, NegedgeStickybit, BothedgeStickybit
+)
+from .hw_write import WEWrite, WELWrite
+
+if TYPE_CHECKING:
+    from systemrdl.node import FieldNode
+
+
+class StickyWE(Sticky, WEWrite):
+    """
+    Normal multi-bit sticky with write enable
+    """
+    comment = "multi-bit sticky with WE"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return (
+            Sticky.is_match(self, field)
+            and WEWrite.is_match(self, field)
+        )
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = Sticky.get_predicate(self, field)
+        WE = WEWrite.get_predicate(self, field)
+        return f"{BASE} && {WE}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return Sticky.get_assignments(self, field)
+
+class StickyWEL(Sticky, WELWrite):
+    """
+    Normal multi-bit sticky with write enable low
+    """
+    comment = "multi-bit sticky with WEL"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return (
+            Sticky.is_match(self, field)
+            and WELWrite.is_match(self, field)
+        )
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = Sticky.get_predicate(self, field)
+        WEL = WELWrite.get_predicate(self, field)
+        return f"{BASE} && {WEL}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return Sticky.get_assignments(self, field)
+
+class StickybitWE(Stickybit, WEWrite):
+    """
+    Normal stickybiti with write enable
+    """
+    comment = "stickybit with WE"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return (
+            Stickybit.is_match(self, field)
+            and WEWrite.is_match(self, field)
+        )
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = Stickybit.get_predicate(self, field)
+        WE = WEWrite.get_predicate(self, field)
+        return f"{BASE} && {WE}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return Stickybit.get_assignments(self, field)
+
+class StickybitWEL(Stickybit, WELWrite):
+    """
+    Normal stickybiti with write enable low
+    """
+    comment = "stickybit with WEL"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return Stickybit.is_match(self, field) \
+            and WELWrite.is_match(self, field)
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = Stickybit.get_predicate(self, field)
+        WEL = WELWrite.get_predicate(self, field)
+        return f"{BASE} && {WEL}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return Stickybit.get_assignments(self, field)
+
+class PosedgeStickybitWE(PosedgeStickybit, WEWrite):
+    """
+    Positive edge stickybit with write enable
+    """
+    comment = "posedge stickybit with WE"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return PosedgeStickybit.is_match(self, field) \
+            and WEWrite.is_match(self, field)
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = PosedgeStickybit.get_predicate(self, field)
+        WE = WEWrite.get_predicate(self, field)
+        return f"{BASE} && {WE}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return PosedgeStickybit.get_assignments(self, field)
+
+class PosedgeStickybitWEL(PosedgeStickybit, WELWrite):
+    """
+    Positive edge stickybit with write enable low
+    """
+    comment = "posedge stickybit with WEL"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return PosedgeStickybit.is_match(self, field) \
+            and WELWrite.is_match(self, field)
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = PosedgeStickybit.get_predicate(self, field)
+        WEL = WELWrite.get_predicate(self, field)
+        return f"{BASE} && {WEL}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return PosedgeStickybit.get_assignments(self, field)
+
+class NegedgeStickybitWE(NegedgeStickybit, WEWrite):
+    """
+    Negative edge stickybit with write enable
+    """
+    comment = "negedge stickybit with WE"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return NegedgeStickybit.is_match(self, field) \
+            and WEWrite.is_match(self, field)
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = NegedgeStickybit.get_predicate(self, field)
+        WE = WEWrite.get_predicate(self, field)
+        return f"{BASE} && {WE}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return NegedgeStickybit.get_assignments(self, field)
+
+class NegedgeStickybitWEL(NegedgeStickybit, WELWrite):
+    """
+    Negative edge stickybit with write enable low
+    """
+    comment = "negedge stickybit with WEL"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return NegedgeStickybit.is_match(self, field) \
+            and WELWrite.is_match(self, field)
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = NegedgeStickybit.get_predicate(self, field)
+        WEL = WELWrite.get_predicate(self, field)
+        return f"{BASE} && {WEL}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return NegedgeStickybit.get_assignments(self, field)
+
+class BothedgeStickybitWE(BothedgeStickybit, WEWrite):
+    """
+    edge-sensitive stickybit with write enable
+    """
+    comment = "bothedge stickybit with WE"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return BothedgeStickybit.is_match(self, field) \
+            and WEWrite.is_match(self, field)
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = BothedgeStickybit.get_predicate(self, field)
+        WE = WEWrite.get_predicate(self, field)
+        return f"{BASE} && {WE}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return BothedgeStickybit.get_assignments(self, field)
+
+class BothedgeStickybitWEL(BothedgeStickybit, WELWrite):
+    """
+    edge-sensitive stickybit with write enable low
+    """
+    comment = "bothedge stickybit with WEL"
+    def is_match(self, field: 'FieldNode') -> bool:
+        return BothedgeStickybit.is_match(self, field) \
+            and WELWrite.is_match(self, field)
+
+    def get_predicate(self, field: 'FieldNode') -> str:
+        BASE = BothedgeStickybit.get_predicate(self, field)
+        WEL = WELWrite.get_predicate(self, field)
+        return f"{BASE} && {WEL}"
+
+    def get_assignments(self, field: 'FieldNode') -> List[str]:
+        return BothedgeStickybit.get_assignments(self, field)