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@Gchauvon
Gchauvon committed Jan 31, 2025
1 parent 27976a8 commit 614d6ef
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Showing 4 changed files with 90 additions and 70 deletions.
6 changes: 3 additions & 3 deletions core/commit_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -302,9 +302,9 @@ module commit_stage

if (CVA6Cfg.NrCommitPorts > 1) begin
commit_macro_ack[1] = 1'b0;
commit_ack_o[1] = 1'b0;
we_gpr_o[1] = 1'b0;
wdata_o[1] = commit_instr_i[1].result;
commit_ack_o[1] = 1'b0;
we_gpr_o[1] = 1'b0;
wdata_o[1] = commit_instr_i[1].result;

// -----------------
// Commit Port 2
Expand Down
4 changes: 2 additions & 2 deletions core/cvxif_fu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -66,8 +66,8 @@ module cvxif_fu
always_comb begin
x_exception_o.valid = x_illegal_i;
x_exception_o.cause = x_illegal_i ? riscv::ILLEGAL_INSTR : '0;
if (CVA6Cfg.TvalEn)
x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO.
if (CVA6Cfg.TvalEn)
x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO.
end

endmodule
140 changes: 80 additions & 60 deletions core/id_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -105,50 +105,50 @@ module id_stage #(
} issue_struct_t;
issue_struct_t [CVA6Cfg.NrIssuePorts-1:0] issue_n, issue_q;
// stall required for ZCMP ZCMT CVXIF
logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch;
logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch;

logic [CVA6Cfg.NrIssuePorts-1:0] is_control_flow_instr;
scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instruction;
logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instruction_valid;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr;

// Compressed decoder signals
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_rvc;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_rvc;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_rvc;
logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr;
logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_rvc;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_rvc;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_rvc;
logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr;
logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr;

// CVXIF compressed interface driver signals
// Inputs
logic is_illegal_cvxif_i;
logic [31:0] instruction_cvxif_i;
logic is_compressed_cvxif_i;
logic stall_macro_deco;
logic is_illegal_cvxif_i;
logic [ 31:0] instruction_cvxif_i;
logic is_compressed_cvxif_i;
logic stall_macro_deco;
// Outputs
logic is_illegal_cvxif_o;
logic [31:0] instruction_cvxif_o;
logic is_compressed_cvxif_o;
logic is_illegal_cvxif_o;
logic [ 31:0] instruction_cvxif_o;
logic is_compressed_cvxif_o;

// ZCMP decoder signals
logic is_illegal_zcmp;
logic [31:0] instruction_zcmp;
logic is_compressed_zcmp;
logic stall_macro_deco_zcmp;
logic is_last_macro_instr;
logic is_double_rd_macro_instr;
logic is_illegal_zcmp;
logic [ 31:0] instruction_zcmp;
logic is_compressed_zcmp;
logic stall_macro_deco_zcmp;
logic is_last_macro_instr;
logic is_double_rd_macro_instr;

// ZCMT decoder signals
logic is_illegal_zcmt;
logic [31:0] instruction_zcmt;
logic is_compressed_zcmt;
logic stall_macro_deco_zcmt;
logic [CVA6Cfg.XLEN-1:0] jump_address;
logic is_illegal_zcmt;
logic [ 31:0] instruction_zcmt;
logic is_compressed_zcmt;
logic stall_macro_deco_zcmt;
logic [ CVA6Cfg.XLEN-1:0] jump_address;

// Decoder signals
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_deco;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_deco;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_deco;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_deco;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_deco;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_deco;


if (CVA6Cfg.RVC) begin
Expand All @@ -173,9 +173,9 @@ module id_stage #(
end

if (CVA6Cfg.RVZCMP) begin
macro_decoder #(
macro_decoder #(
.CVA6Cfg(CVA6Cfg)
) macro_decoder_i (
) macro_decoder_i (
.instr_i (instruction_rvc[0]),
.is_macro_instr_i (is_macro_instr[0]),
.clk_i (clk_i),
Expand All @@ -189,11 +189,11 @@ module id_stage #(
.fetch_stall_o (stall_macro_deco_zcmp),
.is_last_macro_instr_o (is_last_macro_instr),
.is_double_rd_macro_instr_o(is_double_rd_macro_instr)
);
);
end else begin
assign instruction_zcmp = instruction_rvc;
assign is_illegal_zcmp = is_illegal_rvc;
assign is_compressed_zcmp = is_compressed_rvc;
assign instruction_zcmp = instruction_rvc;
assign is_illegal_zcmp = is_illegal_rvc;
assign is_compressed_zcmp = is_compressed_rvc;
assign stall_macro_deco_zcmp = '0;
assign is_last_macro_instr = '0;
assign is_double_rd_macro_instr = '0;
Expand Down Expand Up @@ -224,9 +224,9 @@ module id_stage #(
.jump_address_o (jump_address)
);
end else begin
assign instruction_zcmt = instruction_rvc;
assign is_illegal_zcmt = is_illegal_rvc;
assign is_compressed_zcmt = is_compressed_rvc;
assign instruction_zcmt = instruction_rvc;
assign is_illegal_zcmt = is_illegal_rvc;
assign is_compressed_zcmt = is_compressed_rvc;
assign stall_macro_deco_zcmt = '0;
assign jump_address = '0;
end
Expand All @@ -236,7 +236,7 @@ module id_stage #(
assign is_illegal_cvxif_i = is_zcmt_instr[0] ? is_illegal_zcmt : is_illegal_zcmp;
assign is_compressed_cvxif_i = is_zcmt_instr[0] ? is_compressed_zcmt : is_compressed_zcmp;
assign stall_macro_deco = is_zcmt_instr[0] ? stall_macro_deco_zcmt : stall_macro_deco_zcmp;
end else begin // Do not instantiate the mux which is not optimized cross-bondaries
end else begin // Do not instantiate the mux which is not optimized cross-bondaries
assign instruction_cvxif_i = instruction_zcmp;
assign is_illegal_cvxif_i = is_illegal_zcmp;
assign is_compressed_cvxif_i = is_compressed_zcmp;
Expand All @@ -249,22 +249,22 @@ module id_stage #(
.x_compressed_req_t(x_compressed_req_t),
.x_compressed_resp_t(x_compressed_resp_t)
) i_cvxif_compressed_if_driver_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.flush_i (flush_i),
.hart_id_i (hart_id_i),
.is_compressed_i (is_compressed_cvxif_i),
.is_illegal_i (is_illegal_cvxif_i),
.instruction_i (instruction_cvxif_i),
.is_compressed_o (is_compressed_cvxif_o),
.is_illegal_o (is_illegal_cvxif_o),
.instruction_o (instruction_cvxif_o),
.stall_i (stall_macro_deco),
.stall_o (stall_instr_fetch[0]),
.compressed_ready_i (compressed_ready_i),
.compressed_resp_i (compressed_resp_i),
.compressed_valid_o (compressed_valid_o),
.compressed_req_o (compressed_req_o)
.clk_i (clk_i),
.rst_ni (rst_ni),
.flush_i (flush_i),
.hart_id_i (hart_id_i),
.is_compressed_i (is_compressed_cvxif_i),
.is_illegal_i (is_illegal_cvxif_i),
.instruction_i (instruction_cvxif_i),
.is_compressed_o (is_compressed_cvxif_o),
.is_illegal_o (is_illegal_cvxif_o),
.instruction_o (instruction_cvxif_o),
.stall_i (stall_macro_deco),
.stall_o (stall_instr_fetch[0]),
.compressed_ready_i(compressed_ready_i),
.compressed_resp_i (compressed_resp_i),
.compressed_valid_o(compressed_valid_o),
.compressed_req_o (compressed_req_o)
);
end else begin
assign stall_instr_fetch[0] = stall_macro_deco;
Expand Down Expand Up @@ -372,19 +372,34 @@ module id_stage #(
issue_n[1].valid = 1'b0;
end else if (fetch_entry_valid_i[0]) begin
fetch_entry_ready_o[0] = ~stall_instr_fetch[0];
issue_n[0] = '{decoded_instruction_valid[0], decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]};
issue_n[0] = '{
decoded_instruction_valid[0],
decoded_instruction[0],
orig_instr[0],
is_control_flow_instr[0]
};
end
end

if (!issue_n[1].valid) begin
if (fetch_entry_ready_o[0]) begin
if (fetch_entry_valid_i[1]) begin
fetch_entry_ready_o[1] = ~stall_instr_fetch[1];
issue_n[1] = '{decoded_instruction_valid[1], decoded_instruction[1], orig_instr[1], is_control_flow_instr[1]};
issue_n[1] = '{
decoded_instruction_valid[1],
decoded_instruction[1],
orig_instr[1],
is_control_flow_instr[1]
};
end
end else if (fetch_entry_valid_i[0]) begin
fetch_entry_ready_o[0] = ~stall_instr_fetch[0];
issue_n[1] = '{decoded_instruction_valid[0], decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]};
issue_n[1] = '{
decoded_instruction_valid[0],
decoded_instruction[0],
orig_instr[0],
is_control_flow_instr[0]
};
end
end

Expand All @@ -395,7 +410,7 @@ module id_stage #(
end
end else begin
always_comb begin
issue_n = issue_q;
issue_n = issue_q;
fetch_entry_ready_o = '0;
// instruction is not valid if we stall due to ZCMT or CVXIF
decoded_instruction_valid[0] = (CVA6Cfg.RVZCMT && is_zcmt_instr && stall_macro_deco_zcmt) ||
Expand All @@ -409,8 +424,13 @@ module id_stage #(
// or the issue stage is currently acknowledging an instruction, which means that we will have space
// for a new instruction
if (!issue_n[0].valid && fetch_entry_valid_i[0]) begin
fetch_entry_ready_o[0] = ~stall_instr_fetch[0];
issue_n[0] = '{decoded_instruction_valid[0], decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]};
fetch_entry_ready_o[0] = ~stall_instr_fetch[0];
issue_n[0] = '{
decoded_instruction_valid[0],
decoded_instruction[0],
orig_instr[0],
is_control_flow_instr[0]
};
end

// invalidate the pipeline register on a flush
Expand All @@ -428,4 +448,4 @@ module id_stage #(
end
end

endmodule
endmodule
10 changes: 5 additions & 5 deletions core/issue_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -176,11 +176,11 @@ module issue_stage
scoreboard_entry_t [CVA6Cfg.NR_SB_ENTRIES-1:0] sbe;
} forwarding_t;

forwarding_t fwd;
scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0][ 31:0] orig_instr_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_iro_sb;
forwarding_t fwd;
scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_iro_sb;

assign issue_instr_o = issue_instr_sb_iro[0];
assign issue_instr_hs_o = issue_instr_valid_sb_iro[0] & issue_ack_iro_sb[0];
Expand Down

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