feat: update project tt_um_chip_rom from TinyTapeout/tt-chip-rom

Commit: cbc69c5edf0aaddbc88027b7b711aa362aef7164
Workflow: https://github.com/TinyTapeout/tt-chip-rom/actions/runs/7626402631

projects/tt_um_chip_rom/commit_id.json

@@ -1,8 +1,9 @@
 {
-  "app": "Tiny Tapeout tt05 e9812227",
+  "app": "Tiny Tapeout tt06 67529a81",
   "repo": "https://github.com/TinyTapeout/tt-chip-rom",
-  "commit": "dfc689ff36067623d440d764daa6bde27bc80591",
-  "workflow_url": "https://github.com/TinyTapeout/tt-chip-rom/actions/runs/6193865097",
-  "sort_id": 1694753754266,
-  "openlane_version": "OpenLane 7e5a2e9fb274c0a100b4859a927adce7089455ff\n"
+  "commit": "cbc69c5edf0aaddbc88027b7b711aa362aef7164",
+  "workflow_url": "https://github.com/TinyTapeout/tt-chip-rom/actions/runs/7626402631",
+  "sort_id": 1706518670667,
+  "openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
+  "pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"
 }

projects/tt_um_chip_rom/docs/info.md

@@ -1,12 +1,3 @@
-<!---
-
-This file is used to generate your project datasheet. Please fill in the information below and delete any unused
-sections.
-
-You can also include images in this folder and reference them in the markdown. Each image must be less than
-512 kb in size, and the combined size of all images must be less than 1 MB.
--->
-
 ## How it works
 
 ROM memory that contains information about the Tiny Tapeout chip. The ROM is 8-bit wide and 128 bytes long.

projects/tt_um_chip_rom/info.yaml

@@ -4,7 +4,7 @@ project:
   author:       "Uri Shaked"      # Your name
   discord:      "urish"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "ROM with information about the chip"      # One line description of what your project does
-  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.

projects/tt_um_chip_rom/stats/metrics.csv

@@ -0,0 +1,2 @@
+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_chip_rom,wokwi,flow completed,0h1m8s0ms,0h0m53s0ms,2673.391732090503,0.01795472,1336.6958660452515,0.57,86.1857,480.85,24,0,0,0,0,0,0,0,0,0,0,-1,-1,80,96,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,109715.0,0.0,0.0,0.06,0.04,0.0,-1,8,43,8,43,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,1239,225,0,244,24,1732,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_chip_rom/stats/synthesis-stats.txt

@@ -0,0 +1,17 @@
+
+62. Printing statistics.
+
+=== tt_um_chip_rom ===
+
+   Number of wires:                  8
+   Number of wire bits:             43
+   Number of public wires:           8
+   Number of public wire bits:      43
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                 24
+     sky130_fd_sc_hd__conb_1        24
+
+   Chip area for module '\tt_um_chip_rom': 90.086400
+