feat: update project tt_um_MichaelBell_latch_mem from MichaelBell/tt0…

…6-memory

Commit: 10b3e49805b010297b040e70d23f73f0c998ada3
Workflow: https://github.com/MichaelBell/tt06-memory/actions/runs/8758236583

projects/tt_um_MichaelBell_latch_mem/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt06 7f56a586",
   "repo": "https://github.com/MichaelBell/tt06-memory",
-  "commit": "e611b46e65bb7f8a2c2e17bf946a0daf93ed04aa",
-  "workflow_url": "https://github.com/MichaelBell/tt06-memory/actions/runs/8757526708",
+  "commit": "10b3e49805b010297b040e70d23f73f0c998ada3",
+  "workflow_url": "https://github.com/MichaelBell/tt06-memory/actions/runs/8758236583",
   "sort_id": 1713476062118,
   "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_MichaelBell_latch_mem/docs/info.md

@@ -6,17 +6,60 @@ Resetting the project does not reset the RAM contents.
 
 ## How to test
 
-To write a byte to memory:
+To read a byte from memory:
 
 * Set the `addr` pins to the desired address and set `wr_en` low
 * Pulse `clk`
-* Keep the `addr` pins set, set `data_in` (the bidirectional pins) to the desired value, set `wr_en` high
-* Pulse `clk`
-* The memory location is now written.
-* Note the next cycle must have `wr_en` low.
+* `data_out` (the output pins) reads the value at the memory location.
 
-To read a byte from memory:
+To write a byte to memory:
 
-* Set the `addr` pins to the desired address and set `wr_en` low
+* Set the `addr` pins to the desired address, set `data_in` (the bidirectional pins) to the desired value, and set `wr_en` high
 * Pulse `clk`
-* `data_out` (the output pins) reads the value at the memory location.
+* The memory location will be written on the next cycle.  The `data_out` pins will now read the old value at this address.
+* The next cycle can not be a write.  
+
+On the cycle immediately after a write the value of `wr_en` and `data_in` will be ignored - the cycle is always a read.  If `addr` is left the same then the value read will be the value just written to that location.
+
+## How it works
+
+Setting values into latches reliably is a little tricky.  There are two important considerations:
+
+* The latch gate must only go high for the latches for the byte that is addressed.  The other latch gates must not glitch.
+* The data must be stable until the latch gate is definitely low again.
+
+To ensure the restrictions are met, writes take 2 cycles, and only 1 write can be in flight at once, so the cycle after any write is always treated as a read.
+
+The scheme used is described in detail below.
+
+### Writing: Ensuring stable inputs to the latches.
+
+The write address, `addr_write`, is always set to the same value for 2 clocks when doing a write.
+When the write is requested `addr_write` and `data_to_write` are captured.  `wr_en_next` is set high.
+If `wr_en_next` was already high the write is ignored, so the inputs to the latches aren't 
+modified when a write is about to happen.
+
+On the next clock, `wr_en_valid` is set to `wr_en_next`.  `addr_write` is stable at this time so the
+`sel_byte` wires, that contain the result of the comparison of the write address with the byte address for each latch, will already be stable at the point `wr_en_valid` goes high.
+
+`wr_en_ok` is a negative edge triggered flop that is set to `!wr_en_valid`.  This will therefore
+go low half a clock after `wr_en_valid` is set high.  And because two consecutive writes are not
+allowed it will always be high when `wr_en_valid` goes high.
+
+The latch gate is set by `and`ing together `wr_en_valid`, `wr_en_ok` and the `sel_byte` for that byte.
+This means the latch gate for just the selected byte's latches goes high for the first half of
+the write clock cycle.  data_to_write is stable across this time (it can not change until the
+next clock rising edge), so will be cleanly captured by the latch when the latch gate goes low.
+
+### Reading: Mux and tri-state buffer.
+
+Reading the latches is straightforward.  However, a 64:1 mux for each bit is relatively area 
+intensive, so instead for each bit we have 4 16:1 muxes feeding 4 tri-state buffers.
+
+Only the tri-state buffer corresponding to the selected read address is enabled, and the output is
+taken from the wire driven by those 4 buffers.
+
+To minimize contention, the tri-state enable pin of the buffers is driven directly from a flop which
+captures the selected read address directly from the inputs, at the same cycle as the `addr_read` flops are set.
+
+The combined output wire then goes to a final buffer before leaving the module, ensuring the outputs are driven cleanly.

projects/tt_um_MichaelBell_latch_mem/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_MichaelBell_latch_mem,wokwi,flow completed,0h4m33s0ms,0h4m5s0ms,138348.02213568354,0.01795472,69174.01106784177,83.91,85.6395,602.29,1147,0,0,0,0,0,0,0,1,1,0,-1,-1,44962,10293,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,24800186.0,0.0,77.32,68.22,34.45,24.92,-1,1274,1816,158,700,0,0,0,1790,2,1,13,0,579,0,0,32,550,118,8,321,225,3,378,1242,2169,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.85,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_MichaelBell_latch_mem,wokwi,flow completed,0h5m16s0ms,0h4m47s0ms,146590.97997629593,0.01795472,73295.48998814797,86.37,87.58160000000001,586.16,1210,0,0,0,0,0,0,0,1,1,0,-1,-1,48106,10851,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,24748432.0,0.0,78.29,69.56,38.5,28.58,-1,1266,1808,223,765,0,0,0,1782,18,1,7,15,494,0,0,32,550,119,8,270,225,15,385,1316,2211,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.88,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_MichaelBell_latch_mem/stats/synthesis-stats.txt

@@ -3,18 +3,20 @@
 
 === tt_um_MichaelBell_latch_mem ===
 
-   Number of wires:               1107
-   Number of wire bits:           1142
-   Number of public wires:         649
-   Number of public wire bits:     684
+   Number of wires:               1170
+   Number of wire bits:           1205
+   Number of public wires:         714
+   Number of public wire bits:     749
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:               1147
-     sky130_fd_sc_hd__a2111o_2       8
-     sky130_fd_sc_hd__a221o_2       92
-     sky130_fd_sc_hd__a22o_2       156
-     sky130_fd_sc_hd__and2_2         2
+   Number of cells:               1210
+     sky130_fd_sc_hd__a2111o_2       9
+     sky130_fd_sc_hd__a211o_2        1
+     sky130_fd_sc_hd__a221o_2       81
+     sky130_fd_sc_hd__a22o_2       166
+     sky130_fd_sc_hd__and2_1        64
+     sky130_fd_sc_hd__and2_2         3
      sky130_fd_sc_hd__and4_2         1
      sky130_fd_sc_hd__and4b_2        4
      sky130_fd_sc_hd__and4bb_2       6
@@ -27,22 +29,23 @@
      sky130_fd_sc_hd__inv_2          2
      sky130_fd_sc_hd__mux2_2        14
      sky130_fd_sc_hd__nand2_2        3
-     sky130_fd_sc_hd__nand4_2        2
+     sky130_fd_sc_hd__nand4_2        1
      sky130_fd_sc_hd__nand4b_2       2
      sky130_fd_sc_hd__nor2_2        64
      sky130_fd_sc_hd__nor2b_2        1
      sky130_fd_sc_hd__nor4_2         1
      sky130_fd_sc_hd__nor4b_2        4
      sky130_fd_sc_hd__o22a_2         8
-     sky130_fd_sc_hd__or2_2         19
-     sky130_fd_sc_hd__or2b_2         2
-     sky130_fd_sc_hd__or3_2         26
-     sky130_fd_sc_hd__or3b_2         4
-     sky130_fd_sc_hd__or4_2         16
+     sky130_fd_sc_hd__or2_2         14
+     sky130_fd_sc_hd__or2b_2         4
+     sky130_fd_sc_hd__or3_2         24
+     sky130_fd_sc_hd__or3b_2         2
+     sky130_fd_sc_hd__or4_2         21
      sky130_fd_sc_hd__or4b_2         4
      sky130_fd_sc_hd__or4bb_2        5
 
+   Area for cell type \sky130_fd_sc_hd__and2_1 is unknown!
    Area for cell type \sky130_fd_sc_hd__clkbuf_4 is unknown!
 
-   Chip area for module '\tt_um_MichaelBell_latch_mem': 13297.753600
+   Chip area for module '\tt_um_MichaelBell_latch_mem': 13288.995200
 

projects/tt_um_MichaelBell_latch_mem/tt_um_MichaelBell_latch_mem.lef

@@ -68,6 +68,7 @@ MACRO tt_um_MichaelBell_latch_mem
     DIRECTION INPUT ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.196500 ;
+    ANTENNADIFFAREA 0.434700 ;
     PORT
       LAYER met4 ;
         RECT 151.190 110.520 151.490 111.520 ;
@@ -104,6 +105,7 @@ MACRO tt_um_MichaelBell_latch_mem
     DIRECTION INPUT ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.196500 ;
+    ANTENNADIFFAREA 0.434700 ;
     PORT
       LAYER met4 ;
         RECT 136.470 110.520 136.770 111.520 ;
@@ -122,6 +124,7 @@ MACRO tt_um_MichaelBell_latch_mem
     DIRECTION INPUT ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.213000 ;
+    ANTENNADIFFAREA 0.434700 ;
     PORT
       LAYER met4 ;
         RECT 129.110 110.520 129.410 111.520 ;
@@ -148,6 +151,7 @@ MACRO tt_um_MichaelBell_latch_mem
     DIRECTION INPUT ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.196500 ;
+    ANTENNADIFFAREA 0.434700 ;
     PORT
       LAYER met4 ;
         RECT 118.070 110.520 118.370 111.520 ;
@@ -417,35 +421,14 @@ MACRO tt_um_MichaelBell_latch_mem
     END
   END uo_out[7]
   OBS
-      LAYER nwell ;
-        RECT 2.570 107.385 158.430 108.990 ;
-        RECT 2.570 101.945 158.430 104.775 ;
-        RECT 2.570 96.505 158.430 99.335 ;
-        RECT 2.570 91.065 158.430 93.895 ;
-        RECT 2.570 85.625 158.430 88.455 ;
-        RECT 2.570 80.185 158.430 83.015 ;
-        RECT 2.570 74.745 158.430 77.575 ;
-        RECT 2.570 69.305 158.430 72.135 ;
-        RECT 2.570 63.865 158.430 66.695 ;
-        RECT 2.570 58.425 158.430 61.255 ;
-        RECT 2.570 52.985 158.430 55.815 ;
-        RECT 2.570 47.545 158.430 50.375 ;
-        RECT 2.570 42.105 158.430 44.935 ;
-        RECT 2.570 36.665 158.430 39.495 ;
-        RECT 2.570 31.225 158.430 34.055 ;
-        RECT 2.570 25.785 158.430 28.615 ;
-        RECT 2.570 20.345 158.430 23.175 ;
-        RECT 2.570 14.905 158.430 17.735 ;
-        RECT 2.570 9.465 158.430 12.295 ;
-        RECT 2.570 4.025 158.430 6.855 ;
       LAYER li1 ;
         RECT 2.760 2.635 158.240 108.885 ;
       LAYER met1 ;
-        RECT 2.760 0.720 160.470 111.480 ;
+        RECT 2.370 0.040 160.930 111.480 ;
       LAYER met2 ;
-        RECT 4.230 0.690 160.440 111.510 ;
+        RECT 2.400 0.010 160.910 111.510 ;
       LAYER met3 ;
-        RECT 3.950 2.555 159.030 110.665 ;
+        RECT 3.950 2.555 160.935 110.665 ;
       LAYER met4 ;
         RECT 4.690 110.120 7.270 111.170 ;
         RECT 8.370 110.120 10.950 111.170 ;
@@ -489,14 +472,14 @@ MACRO tt_um_MichaelBell_latch_mem
         RECT 148.210 110.120 150.790 111.170 ;
         RECT 151.890 110.120 154.470 111.170 ;
         RECT 3.975 109.440 155.185 110.120 ;
-        RECT 3.975 6.295 20.995 109.440 ;
-        RECT 23.395 6.295 40.430 109.440 ;
-        RECT 42.830 6.295 59.865 109.440 ;
-        RECT 62.265 6.295 79.300 109.440 ;
-        RECT 81.700 6.295 98.735 109.440 ;
-        RECT 101.135 6.295 118.170 109.440 ;
-        RECT 120.570 6.295 137.605 109.440 ;
-        RECT 140.005 6.295 155.185 109.440 ;
+        RECT 3.975 4.255 20.995 109.440 ;
+        RECT 23.395 4.255 40.430 109.440 ;
+        RECT 42.830 4.255 59.865 109.440 ;
+        RECT 62.265 4.255 79.300 109.440 ;
+        RECT 81.700 4.255 98.735 109.440 ;
+        RECT 101.135 4.255 118.170 109.440 ;
+        RECT 120.570 4.255 137.605 109.440 ;
+        RECT 140.005 4.255 155.185 109.440 ;
   END
 END tt_um_MichaelBell_latch_mem
 END LIBRARY