feat: update project tt_um_levenshtein from peter-noerlund/tt09-leven…

…shtein Commit: 0257a1fbd8412b06379777ab3d6752099b7a3bed Workflow: https://github.com/peter-noerlund/tt09-levenshtein/actions/runs/11163130335
TinyTapeout · Oct 3, 2024 · dabfd46 · dabfd46
1 parent 26d5e73
commit dabfd46
Show file tree

Hide file tree

Showing 8 changed files with 7,558 additions and 6,683 deletions.
diff --git a/projects/tt_um_levenshtein/commit_id.json b/projects/tt_um_levenshtein/commit_id.json
@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 30dbb0cd",
   "repo": "https://github.com/peter-noerlund/tt09-levenshtein",
-  "commit": "335c793535c384ab37ef0727ebcf1e9118ee2db1",
-  "workflow_url": "https://github.com/peter-noerlund/tt09-levenshtein/actions/runs/11111357389",
+  "commit": "0257a1fbd8412b06379777ab3d6752099b7a3bed",
+  "workflow_url": "https://github.com/peter-noerlund/tt09-levenshtein/actions/runs/11163130335",
   "sort_id": 1727039658434,
   "openlane_version": "OpenLane2 2.1.7",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

diff --git a/projects/tt_um_levenshtein/docs/info.md b/projects/tt_um_levenshtein/docs/info.md
@@ -59,13 +59,16 @@ As indicated by the SPI protocol, the address space is 23 bits.
 
 The address space is basically as follows:
 
-| Address  | Size | Access | Identifier  |
-|----------|------|--------|-------------|
-| 0x000000 | 1    | R/W    | `CTRL`      |
-| 0x000001 | 1    | R/O    | `DISTANCE`  |
-| 0x000002 | 2    | R/O    | `INDEX`     |
-| 0x000200 | 512  | R/W    | `VECTORMAP` |
-| 0x000400 | 8M   | R/W    | `DICT`      |
+| Address  | Size | Access | Identifier   |
+|----------|------|--------|--------------|
+| 0x000000 | 1    | R/W    | `CTRL`       |
+| 0x000001 | 1    | R/W    | `SRAM_CTRL`  |
+| 0x000002 | 1    | R/W    | `LENGTH`     |
+| 0x000003 | 1    | R/O    | `MAX_LENGTH` |
+| 0x000004 | 2    | R/O    | `INDEX`      |
+| 0x000006 | 1    | R/O    | `DISTANCE`   |
+| 0x000400 | 768  | R/W    | `VECTORMAP`  |
+| 0x000800 | 8M   | R/W    | `DICT`       |
 
 **CTRL**
 
@@ -75,11 +78,45 @@ The layout is as follows:
 
 | Bits | Size | Access | Description                                                 |
 |------|------|--------|-------------------------------------------------------------|
-| 0-4  | 4    | R/W    | Word length                                                 |
-| 5-6  | 2    | R/O    | Not used                                                    |
-| 7    | 1    | R/O    | Is set to `1` while the engine runs and `0` when it is done |
+| 0    | 1    | R/W    | Enable flag                                                 |
+| 1-7  | 7    | R/O    | Not used                                                    |
 
-When data is written to this address, the engine automatically starts.
+Set the enable flag to start the engine. When the engine is finished, the enable flag is changed to `0`
+
+**SRAM_CTRL**
+
+Controls the SRAM
+
+| Bits | Size | Access | Description                                                 |
+|------|------|--------|-------------------------------------------------------------|
+| 0-1  | 2    | R/W    | Chip select                                                 |
+| 2-7  | 6    | R/O    | Not used                                                    |
+
+The chip select flag controls which chip select is used on the PMOD when accessing SRAM
+
+| Value | Pin    | Notes                                                                           |
+|-------|--------|---------------------------------------------------------------------------------|
+| 0     | _None_ | Default value                                                                   |
+| 1     | CS     | Uses the default CS on the PMOD (Pin 1). Compatible with Machdyne's QQSPI PSRAM |
+| 2     | CS2    | Uses CS2 on the PMOD (pin 6). Compatible with mole99's QSPI Flash/(P)SRAM       |
+| 3     | CS3    | Uses CS3 on the PMOD (pin 7). Compatible with mole99's QSPI Flash/(P)SRAM       |
+
+**LENGTH**
+
+| Bits | Size | Access | Description                                                 |
+|------|------|--------|-------------------------------------------------------------|
+| 0-7  | 8    | R/W    | Word length minus 1                                         |
+
+Used to indicate the length of the search word. Note that the word cannot be empty and it cannot
+exceed 20 characters.
+
+**MAX_LENGTH**
+
+| Bits | Size | Access | Description                       |
+|------|------|--------|-----------------------------------|
+| 0-7  | 8    | R/O    | Max word length supported minus 1 |
+
+This field allows for applications to dynamically detect the size of the bit vector.
 
 **DISTANCE**
 
@@ -95,19 +132,29 @@ The vector map must contain the corresponding bitvector for each input byte in t
 
 If the search word is `application`, the bit vectors will look as follows:
 
-| Letter | Index  | Bit vector                              |
-|--------|--------|-----------------------------------------|
-| `a`    | `0x61` | `16'b00000000_01000001` (`a_____a____`) |
-| `p`    | `0x70` | `16'b00000000_00000110` (`_pp________`) |
-| `l`    | `0x6C` | `16'b00000000_00001000` (`___l_______`) |
-| `i`    | `0x69` | `16'b00000001_00010000` (`____i___i__`) |
-| `c`    | `0x63` | `16'b00000000_00100000` (`_____c_____`) |
-| `t`    | `0x74` | `16'b00000000_10000000` (`_______t___`) |
-| `o`    | `0x6F` | `16'b00000010_00000000` (`_________o_`) |
-| `n`    | `0x6E` | `16'b00000100_00000000` (`__________n`) |
-| *      | *      | `16'b00000000_00000000` (`___________`) |
+| Letter | Index  | Bit vector                                   |
+|--------|--------|----------------------------------------------|
+| `a`    | `0x61` | `20'b0000_00000000_01000001` (`a_____a____`) |
+| `p`    | `0x70` | `20'b0000_00000000_00000110` (`_pp________`) |
+| `l`    | `0x6C` | `20'b0000_00000000_00001000` (`___l_______`) |
+| `i`    | `0x69` | `20'b0000_00000001_00010000` (`____i___i__`) |
+| `c`    | `0x63` | `20'b0000_00000000_00100000` (`_____c_____`) |
+| `t`    | `0x74` | `20'b0000_00000000_10000000` (`_______t___`) |
+| `o`    | `0x6F` | `20'b0000_00000010_00000000` (`_________o_`) |
+| `n`    | `0x6E` | `20'b0000_00000100_00000000` (`__________n`) |
+| *      | *      | `20'b0000_00000000_00000000` (`___________`) |
 
-Since each vector is 16-bit, the corresponding address is `0x200 + index * 2`
+Each vector represents 20 bits, stored as a 24-bit vector, aligned to 32 bits.
+
+Example based on the `application` bit vectors:
+
+| Address | Letter       | Bytes         |
+|---------|--------------|---------------|
+| 000584  | `a` (U+0061) | `x0 00 61 xx` |
+| 000588  | `b` (U+0062) | `x0 00 00 xx` |
+| 00058C  | `c` (U+0063) | `x0 00 20 xx` |
+
+The vectormap is stored in SRAM so the values are indetermined at power up and must be cleared.
 
 **DICT**
 
@@ -131,18 +178,22 @@ cmake --build build
 Next, you can run the test tool:
 
 ```sh
-./build/client/client --device tt09 --test
+# Machdyne QQSPI PSRAM
+./build/client/client --device tt --cs cs --test
+
+# mole99 PSRAM
+./build/client/client --device tt --cs cs2 --test
 ```
 
 This will load 1024 words of random length and characters into the SRAM and then perform a bunch of searches, verifying that the returned result is correct.
 
 ## External hardware
 
-To operate, the device needs an SPI PSRAM PMOD. The design is tested with the QQSPI PSRAM PMOD from Machdyne, but any memory PMOD will work as long as it supports:
+To operate, the device needs an QSPI PSRAM PMOD. The design is tested with the QQSPI PSRAM PMOD from Machdyne, but any memory PMOD will work as long as it supports:
 
-* WRITE (`0x02`) with no latency
-* READ (`0x03`) with no latency
+* WRITE QUAD with the command `0x38` in 1S-4S-4S mode and no latency
+* FAST READ QUAD with the command `0xE8` in 1S-4S-4S mode and 6 wait cycles
 * 24-bit addresses
-* Uses pin 0 for `SS#`.
+* Uses pin 0, 6, or 7 for `SS#`.
 
-Note, that this makes the SRAM/Flash PMOD from mole99 incompatible, but the spi-ram-emu project for the RP2040 can be used if it is changed to 24-bit adressing (It can just ignore the eight most significant bits)
+Note that this makes it incompatible with the spi-ram-emu project for the RP2040.
diff --git a/projects/tt_um_levenshtein/info.yaml b/projects/tt_um_levenshtein/info.yaml
@@ -4,7 +4,7 @@ project:
   author:       "Peter Nørlund"      # Your name
   discord:      "pchri03."      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "A levenshtein based fuzzy search engine"      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  language:     "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     50000000 # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
@@ -47,14 +47,14 @@ pinout:
   uo[7]: "SPI MISO"
 
   # Bidirectional pins
-  uio[0]: "SRAM SPI SS#"
-  uio[1]: "SRAM SPI MOSI"
-  uio[2]: "SRAM SPI MISO"
-  uio[3]: "SRAM SPI SCK"
-  uio[4]: ""
-  uio[5]: ""
-  uio[6]: ""
-  uio[7]: ""
+  uio[0]: "SRAM QSPI CS"
+  uio[1]: "SRAM QSPI SIO0/MOSI"
+  uio[2]: "SRAM QSPI SIO1/MISO"
+  uio[3]: "SRAM QSPI SCK"
+  uio[4]: "SRAM QSPI SIO2"
+  uio[5]: "SRAM QSPI SIO3"
+  uio[6]: "SRAM QSPI CS2"
+  uio[7]: "SRAM QSPI CS3"
 
 # Do not change!
 yaml_version: 6