Make it a Chisel template

.github/workflows/docs.yaml

@@ -12,6 +12,14 @@ jobs:
         uses: actions/checkout@v4
         with:
           submodules: recursive
+      - name: Set up JDK 11
+        uses: actions/setup-java@v4
+        with:
+          java-version: '11'
+          distribution: 'temurin'
+          cache: 'sbt'
+      - name: generate Verilog
+        run: sbt run
 
       - name: Build docs
         uses: TinyTapeout/tt-gds-action/docs@tt09

.github/workflows/gds.yaml

@@ -12,7 +12,14 @@ jobs:
         uses: actions/checkout@v4
         with:
           submodules: recursive
-
+      - name: Set up JDK 11
+        uses: actions/setup-java@v4
+        with:
+          java-version: '11'
+          distribution: 'temurin'
+          cache: 'sbt'
+      - name: generate Verilog
+        run: sbt run
       - name: Build GDS
         uses: TinyTapeout/tt-gds-action@tt09
         with:
@@ -33,7 +40,14 @@ jobs:
         uses: actions/checkout@v4
         with:
           submodules: recursive
-
+      - name: Set up JDK 11
+        uses: actions/setup-java@v4
+        with:
+          java-version: '11'
+          distribution: 'temurin'
+          cache: 'sbt'
+      - name: generate Verilog
+        run: sbt run
       - name: GL test
         uses: TinyTapeout/tt-gds-action/gl_test@tt09
 

.github/workflows/test.yaml

@@ -23,6 +23,15 @@ jobs:
         shell: bash
         run: pip install -r test/requirements.txt
 
+      - name: Set up JDK 11
+        uses: actions/setup-java@v4
+        with:
+          java-version: '11'
+          distribution: 'temurin'
+          cache: 'sbt'
+      - name: generate Verilog
+        run: sbt run
+
       - name: Run tests
         run: |
           cd test

Makefile

@@ -0,0 +1,13 @@
+
+# Test the Chisel design
+run-test:
+	sbt test
+
+# generate the Verilog
+run-verilog:
+	sbt run
+
+# Configure the Basys3 with open source tools
+
+config:
+	openocd -f 7series.txt

README.md

@@ -4,18 +4,21 @@
 
 - [Read the documentation for project](docs/info.md)
 
+This template is intended for projects written in the Chisel hardware construction language.
+To learn more about Chisel, visit the [Chisel website](https://www.chisel-lang.org/)
+or read the free [Chisel book](http://www.imm.dtu.dk/~masca/chisel-book.html).
 ## What is Tiny Tapeout?
 
 Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.
 
 To learn more and get started, visit https://tinytapeout.com.
 
-## Set up your Verilog project
+## Chisel Projects
 
-1. Add your Verilog files to the `src` folder.
-2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).
+1. Add your Chisel files to the `src` folder and below according the `sbt` conventions.
+2. Edit the [info.yaml](info.yaml) and update information about your project
 3. Edit [docs/info.md](docs/info.md) and add a description of your project.
-4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information.
+4. Optionally, add a testbench to the `test` folder. See [test/README.md](test/README.md) for more information.
 
 The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).
 

info.yaml

@@ -4,7 +4,7 @@ project:
   author:       ""      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  language:     "Chisel" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
@@ -17,7 +17,8 @@ project:
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "project.v"
+    - "tt_um_chisel_template.v"
+    - "ChiselTop.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/main/scala/ChiselTop.scala

@@ -0,0 +1,37 @@
+import chisel3._
+
+/**
+ * Example design in Chisel.
+ * A redesign of the Tiny Tapeout example.
+ */
+class ChiselTop() extends Module {
+  val io = IO(new Bundle {
+    val ui_in = Input(UInt(8.W))      // Dedicated inputs
+    val uo_out = Output(UInt(8.W))    // Dedicated outputs
+    val uio_in = Input(UInt(8.W))     // IOs: Input path
+    val uio_out = Output(UInt(8.W))   // IOs: Output path
+    val uio_oe = Output(UInt(8.W))    // IOs: Enable path (active high: 0=input, 1=output)
+    val ena = Input(Bool())           // will go high when the design is enabled
+  })
+
+  io.uio_out := 0.U
+  // use bi-directionals as input
+  io.uio_oe := 0.U
+
+  val add = WireDefault(0.U(7.W))
+  add := io.ui_in + io.uio_in
+
+  // Blink with 1 Hzq
+  val cntReg = RegInit(0.U(32.W))
+  val ledReg = RegInit(0.U(1.W))
+  cntReg := cntReg + 1.U
+  when (cntReg === 25000000.U) {
+    cntReg := 0.U
+    ledReg := ~ledReg
+  }
+  io.uo_out := ledReg ## add
+}
+
+object ChiselTop extends App {
+  emitVerilog(new ChiselTop(), Array("--target-dir", "src"))
+}

src/tt_um_chisel_template.v

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2024 Your Name
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`define default_netname none
+
+module tt_um_example (
+    input  wire [7:0] ui_in,    // Dedicated inputs
+    output wire [7:0] uo_out,   // Dedicated outputs
+    input  wire [7:0] uio_in,   // IOs: Input path
+    output wire [7:0] uio_out,  // IOs: Output path
+    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
+    input  wire       ena,      // will go high when the design is enabled
+    input  wire       clk,      // clock
+    input  wire       rst_n     // reset_n - low to reset
+);
+
+  // All output pins must be assigned. If not used, assign to 0.
+  // assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
+  // assign uio_out = 0;
+  // assign uio_oe  = 0;
+    wire reset = !rst_n;
+    // Just wrap the Chisel generated Verilog
+
+    ChiselTop ChiselTop(.clock(clk),
+      .reset(reset),
+      .io_ui_in(ui_in),
+      .io_uo_out(uo_out),
+      .io_uio_in(uio_in),
+      .io_uio_out(uio_out),
+      .io_uio_oe(uio_oe),
+      .io_ena(ena));
+
+endmodule

test/Makefile

@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = tt_um_chisel_template.v ChiselTop.v
 
 ifneq ($(GATES),yes)
 

test/README.md

@@ -10,6 +10,12 @@ See below to get started or for more information, check the [website](https://ti
 
 ## How to run
 
+First generate the Chisel Verilog output by running in the project root:
+
+```sh
+sbt run
+```
+
 To run the RTL simulation:
 
 ```sh