pipelinecpu

5-stage pipeline cpu which can achieve 50 mips instructions writing by verilog...

Addressing hazard by applying stall and forward methods.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
ALU.v		ALU.v
Adder.v		Adder.v
DM.v		DM.v
EXT.v		EXT.v
GRF.v		GRF.v
IFU.v		IFU.v
Mul.v		Mul.v
Mux.v		Mux.v
Mux8.v		Mux8.v
NPC.v		NPC.v
P7_standard_timer_2019.v		P7_standard_timer_2019.v
README.md		README.md
ROM1k32bit.v		ROM1k32bit.v
bridge.v		bridge.v
control.v		control.v
datapath.v		datapath.v
forwardCtrl.v		forwardCtrl.v
instru_classification.v		instru_classification.v
loadEx.v		loadEx.v
mips.v		mips.v
regEXMEM.v		regEXMEM.v
regIDEX.v		regIDEX.v
regIFID.v		regIFID.v
regMEMWB.v		regMEMWB.v
saveEx.v		saveEx.v
stop.v		stop.v