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bad value in ADC prescaller for 8 MHz version
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oploc committed Feb 23, 2023
1 parent 33d93b3 commit dc1e4cd
Showing 1 changed file with 5 additions and 13 deletions.
18 changes: 5 additions & 13 deletions fw/LABDOS/LABDOS.ino
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
#define VERSION "06"
#define VERSION "07"
#ifndef CHANNELS
#define CHANNELS 1024 // number of channels in buffer for histogram, including negative numbers (512 or 1024)
#endif
Expand Down Expand Up @@ -181,14 +181,6 @@ void setup()

Serial.println("#Cvak...");

ADMUX = (analog_reference << 6) | ((PIN | 0x10) & 0x1F);
ADCSRB = 0; // Switching ADC to Free Running mode
sbi(ADCSRA, ADATE); // ADC autotrigger enable (mandatory for free running mode)
sbi(ADCSRA, ADSC); // ADC start the first conversions
sbi(ADCSRA, 2); // 0x111 = clock divided by 128, 125 kHz, 104 us for 13 cycles of one AD conversion, 12 us for 1.5 cycle for sample-hold
sbi(ADCSRA, 1);
sbi(ADCSRA, 0);

pinMode(RESET, OUTPUT); // reset for peak detetor

//pinMode(SDpower1, OUTPUT); // SDcard interface
Expand Down Expand Up @@ -223,9 +215,9 @@ void setup()
sbi(ADCSRA, ADATE); // ADC autotrigger enable (mandatory for free running mode)
sbi(ADCSRA, ADSC); // ADC start the first conversions
#if F_CPU==8000000L
cbi(ADCSRA, 2); // 0x111 = clock divided by 64
sbi(ADCSRA, 2); // 0x110 = clock divided by 64
sbi(ADCSRA, 1);
sbi(ADCSRA, 0);
cbi(ADCSRA, 0);
#else
sbi(ADCSRA, 2); // 0x111 = clock divided by 128
sbi(ADCSRA, 1);
Expand Down Expand Up @@ -383,9 +375,9 @@ void loop()
sbi(ADCSRA, ADATE); // ADC autotrigger enable (mandatory for free running mode)
sbi(ADCSRA, ADSC); // ADC start the first conversions
#if F_CPU==8000000L
cbi(ADCSRA, 2); // 0x111 = clock divided by 64
sbi(ADCSRA, 2); // 0x110 = clock divided by 64
sbi(ADCSRA, 1);
sbi(ADCSRA, 0);
cbi(ADCSRA, 0);
#else
sbi(ADCSRA, 2); // 0x111 = clock divided by 128
sbi(ADCSRA, 1);
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