Update and fix spec doc modulo numerics/exec

Wasm-DSL · Oct 3, 2024 · 75ea7be · 75ea7be
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diff --git a/document/core/appendix/changes.rst b/document/core/appendix/changes.rst
@@ -526,26 +526,26 @@ Relaxed Vector Instructions
 Added new *relaxed* vector instructions,
 whose behaviour is non-deterministic and implementation-dependent. [#proposal-relaxed]_
 
-* New binary :ref:`vector instruction <syntax-instr-relaxed>`:
+* New binary :ref:`vector instruction <syntax-instr-vec-relaxed>`:
 
   - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_min}`
   - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_max}`
   - :math:`\K{i16x8.relaxed\_q15mulr\_s}`
   - :math:`\K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s}`
 
-* New ternary :ref:`vector instruction <syntax-instr-relaxed>`:
+* New ternary :ref:`vector instruction <syntax-instr-vec-relaxed>`:
 
   - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_madd}`
   - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_nmadd}`
   - :math:`\K{i}\!N\!\K{x}\!M\!\K{.relaxed\_laneselect}`
   - :math:`\K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}`
 
-* New conversion :ref:`vector instructions <syntax-instr-relaxed>`:
+* New conversion :ref:`vector instructions <syntax-instr-vec-relaxed>`:
 
   - :math:`\K{i32x4.relaxed\_trunc\_f32x4\_}\sx`
   - :math:`\K{i32x4.relaxed\_trunc\_f64x2\_}\sx\K{\_zero}`
 
-* New byte reordering :ref:`vector instruction <syntax-instr-relaxed>`:
+* New byte reordering :ref:`vector instruction <syntax-instr-vec-relaxed>`:
 
   - :math:`\K{i8x16.relaxed\_swizzle}`
 

diff --git a/document/core/appendix/index-instructions.py b/document/core/appendix/index-instructions.py
@@ -393,7 +393,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
     Instruction(r'\V128.\VSTORE~x~\memarg', r'\hex{FD}~~\hex{0B}', r'[\I32~\V128] \to []', r'valid-vstore', r'exec-vstore'),
     Instruction(r'\V128.\VCONST~\i128', r'\hex{FD}~~\hex{0C}', r'[] \to [\V128]', r'valid-vconst', r'exec-vconst'),
     Instruction(r'\I8X16.\VSHUFFLE~\laneidx^{16}', r'\hex{FD}~~\hex{0D}', r'[\V128~\V128] \to [\V128]', r'valid-vshuffle', r'exec-vshuffle'),
-    Instruction(r'\I8X16.\VSWIZZLE', r'\hex{FD}~~\hex{0E}', r'[\V128~\V128] \to [\V128]', r'valid-vswizzle', r'exec-vswizzle'),
+    Instruction(r'\I8X16.\VSWIZZLE', r'\hex{FD}~~\hex{0E}', r'[\V128~\V128] \to [\V128]', r'valid-vswizzlop', r'exec-vswizzlop'),
     Instruction(r'\I8X16.\VSPLAT', r'\hex{FD}~~\hex{0F}', r'[\I32] \to [\V128]', r'valid-vsplat', r'exec-vsplat'),
     Instruction(r'\I16X8.\VSPLAT', r'\hex{FD}~~\hex{10}', r'[\I32] \to [\V128]', r'valid-vsplat', r'exec-vsplat'),
     Instruction(r'\I32X4.\VSPLAT', r'\hex{FD}~~\hex{11}', r'[\I32] \to [\V128]', r'valid-vsplat', r'exec-vsplat'),
@@ -478,7 +478,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
     Instruction(r'\I8X16.\VABS', r'\hex{FD}~~\hex{60}', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'),
     Instruction(r'\I8X16.\VNEG', r'\hex{FD}~~\hex{61}', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
     Instruction(r'\I8X16.\VPOPCNT', r'\hex{FD}~~\hex{62}', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ipopcnt'),
-    Instruction(r'\I8X16.\VALLTRUE', r'\hex{FD}~~\hex{63}', r'[\V128] \to [\I32]', r'valid-vtestop', r'exec-vtestop'),
+    Instruction(r'\I8X16.\VALLTRUE', r'\hex{FD}~~\hex{63}', r'[\V128] \to [\I32]', r'valid-vtestop', r'exec-vtestop', r'op-inez'),
     Instruction(r'\I8X16.\VBITMASK', r'\hex{FD}~~\hex{64}', r'[\V128] \to [\I32]', r'valid-vbitmask', r'exec-vbitmask'),
     Instruction(r'\I8X16.\VNARROW\K{\_i16x8\_s}', r'\hex{FD}~~\hex{65}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vnarrow'),
     Instruction(r'\I8X16.\VNARROW\K{\_i16x8\_u}', r'\hex{FD}~~\hex{66}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vnarrow'),
@@ -633,26 +633,26 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
     Instruction(r'\I32X4.\VTRUNCSAT\K{\_f64x2\_u\_zero}', r'\hex{FD}~~\hex{FD}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat'),
     Instruction(r'\F64X2.\VCONVERT\K{\_}\LOW\K{\_i32x4\_s}', r'\hex{FD}~~\hex{FE}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert'),
     Instruction(r'\F64X2.\VCONVERT\K{\_}\LOW\K{\_i32x4\_u}', r'\hex{FD}~~\hex{FF}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert'),
-    Instruction(r'\I8X16.\RELAXEDSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_swizzle', r'exec-relaxed_swizzle', r'op-irelaxed_swizzle'),
-    Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'),
-    Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'),
-    Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'),
-    Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'),
-    Instruction(r'\F32X4.\RELAXEDMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_madd'),
-    Instruction(r'\F32X4.\RELAXEDNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_nmadd'),
-    Instruction(r'\F64X2.\RELAXEDMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_madd'),
-    Instruction(r'\F64X2.\RELAXEDNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_nmadd'),
-    Instruction(r'\I8X16.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'),
-    Instruction(r'\I16X8.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'),
-    Instruction(r'\I32X4.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'),
-    Instruction(r'\I64X2.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'),
-    Instruction(r'\F32X4.\RELAXEDMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_min'),
-    Instruction(r'\F32X4.\RELAXEDMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_max'),
-    Instruction(r'\F64X2.\RELAXEDMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_min'),
-    Instruction(r'\F64X2.\RELAXEDMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_max'),
-    Instruction(r'\I16X8.\RELAXEDQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-irelaxed_q15mulr_s'),
-    Instruction(r'\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot'),
-    Instruction(r'\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot_add'),
+    Instruction(r'\I8X16.\VRELAXEDSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vswizzlop', r'exec-vswizzlop'),
+    Instruction(r'\I32X4.\VRELAXEDTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'),
+    Instruction(r'\I32X4.\VRELAXEDTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'),
+    Instruction(r'\I32X4.\VRELAXEDTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'),
+    Instruction(r'\I32X4.\VRELAXEDTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'),
+    Instruction(r'\F32X4.\VRELAXEDMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_madd'),
+    Instruction(r'\F32X4.\VRELAXEDNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_nmadd'),
+    Instruction(r'\F64X2.\VRELAXEDMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_madd'),
+    Instruction(r'\F64X2.\VRELAXEDNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_nmadd'),
+    Instruction(r'\I8X16.\VRELAXEDLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-irelaxed_laneselect'),
+    Instruction(r'\I16X8.\VRELAXEDLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-irelaxed_laneselect'),
+    Instruction(r'\I32X4.\VRELAXEDLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-irelaxed_laneselect'),
+    Instruction(r'\I64X2.\VRELAXEDLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-irelaxed_laneselect'),
+    Instruction(r'\F32X4.\VRELAXEDMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_min'),
+    Instruction(r'\F32X4.\VRELAXEDMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_max'),
+    Instruction(r'\F64X2.\VRELAXEDMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_min'),
+    Instruction(r'\F64X2.\VRELAXEDMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_max'),
+    Instruction(r'\I16X8.\VRELAXEDQ15MULR\K{\_s}', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-irelaxed_q15mulr_s'),
+    Instruction(r'\I16X8.\VRELAXEDDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vrelaxed_dot'),
+    Instruction(r'\I32X4.\VRELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vrelaxed_dot_add'),
     Instruction(None, r'\hex{FD}~\hex{94}~\hex{02} \dots'),
     Instruction(None, r'\hex{FE}'),
     Instruction(None, r'\hex{FF}'),

diff --git a/document/core/appendix/profiles.rst b/document/core/appendix/profiles.rst
@@ -65,7 +65,7 @@ This has the consequence that the respective rule is no longer applicable under
 	   \\&&&
 	     \begin{array}[t]{@{}r@{~}l@{}}
 	     (\iff & F.\AMODULE.\MIMEMS[x] = a \\
-	     \wedge & \X{sz} = |S.\SMEMS[a].\MIDATA|/64\,\F{Ki} \\
+	     \wedge & \X{sz} = |S.\SMEMS[a].\MIDATAS|/64\,\F{Ki} \\
 	     \wedge & S' = S \with \SMEMS[a] = \growmem(S.\SMEMS[a], n)) \\[1ex]
 	     \end{array}
 	   \\[1ex]
@@ -123,7 +123,7 @@ It defines a sub-language that does not exhibit any incidental non-deterministic
 
 * All :ref:`NaN <syntax-nan>` values :ref:`generated <aux-nans>` by :ref:`floating-point instructions <syntax-instr-numeric>` are canonical and positive.
 
-* All :ref:`relaxed vector instructions <syntax-instr-relaxed>` have a fixed behaviour that does not depend on the implementation.
+* All :ref:`relaxed vector instructions <syntax-instr-vec-relaxed>` have a fixed behaviour that does not depend on the implementation.
 
 Even under this profile, the |MEMORYGROW| and |TABLEGROW| instructions technically remain :ref:`non-deterministic <exec-memory.grow>`, in order to be able to indicate resource exhaustion.
 

diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst
@@ -258,6 +258,7 @@ The ${:CONST} instruction for vectors is followed by 16 immediate bytes, which a
 
 $${grammar: Binstr/vec-const}
 
+.. _binary-vswizzlop:
 .. _binary-vshuffle:
 
 The ${:SHUFFLE} instruction is also followed by the encoding of 16 ${:laneidx} immediates.
@@ -309,6 +310,10 @@ $${grammar: {
 .. _binary-vshiftop:
 .. _binary-viunop:
 .. _binary-vibinop:
+.. _binary-viternop:
+.. _binary-viextunop:
+.. _binary-viextbinop:
+.. _binary-viextternop:
 .. _binary-viminmaxop:
 .. _binary-vsatbinop:
 
@@ -342,6 +347,7 @@ $${grammar: {
   Binstr/vec-shift-i32x4
   Binstr/vec-bin-i32x4
   Binstr/vec-extbin-i32x4
+  Binstr/vec-exttern-i32x4
 }}
 
 $${grammar: {
@@ -375,26 +381,26 @@ $${grammar: {Binstr/vec-cvt}}
 .. math::
    \begin{array}{llclll}
    \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
-     \hex{FD}~~256{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDSWIZZLE \\ &&|&
-     \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_s} \\ &&|&
-     \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_u} \\ &&|&
-     \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_s\_zero} \\ &&|&
-     \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_u\_zero} \\ &&|&
-     \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDMADD \\ &&|&
-     \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDNMADD \\ &&|&
-     \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDMADD \\ &&|&
-     \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDNMADD \\ &&|&
-     \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\RELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\RELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDMIN \\ &&|&
-     \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDMAX \\ &&|&
-     \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDMIN \\ &&|&
-     \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDMAX \\ &&|&
-     \hex{FD}~~273{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDQ15MULRS \\ &&|&
-     \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s} \\ &&|&
-     \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s} \\
+     \hex{FD}~~256{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDSWIZZLE \\ &&|&
+     \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_s} \\ &&|&
+     \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_u} \\ &&|&
+     \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_s\_zero} \\ &&|&
+     \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_u\_zero} \\ &&|&
+     \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDMADD \\ &&|&
+     \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDNMADD \\ &&|&
+     \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDMADD \\ &&|&
+     \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDNMADD \\ &&|&
+     \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\VRELAXEDLANESELECT \\ &&|&
+     \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDLANESELECT \\ &&|&
+     \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDLANESELECT \\ &&|&
+     \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\VRELAXEDLANESELECT \\ &&|&
+     \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDMIN \\ &&|&
+     \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDMAX \\ &&|&
+     \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDMIN \\ &&|&
+     \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDMAX \\ &&|&
+     \hex{FD}~~273{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDQ15MULR\K{\_s} \\ &&|&
+     \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDDOT\K{\_i8x16\_i7x16\_s} \\ &&|&
+     \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDDOT\K{\_i8x16\_i7x16\_add\_s} \\
    \end{array}