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Binary format for SIMD instructions
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@702fbtngus
702fbtngus committed Feb 22, 2024
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302 changes: 302 additions & 0 deletions spectec/spec/wasm-2.0/A-binary.watsup
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Expand Up @@ -437,6 +437,308 @@ grammar Binstr/numeric-extend : instr = ...
| ...


;; Vector instructions

grammar Blaneidx : laneidx =
| l:Bbyte => l

grammar Binstr/vector-memory : instr = ...
| 0xFD 0:Bu32 mo:Bmemop => VLOAD mo
| 0xFD 1:Bu32 mo:Bmemop => VLOAD (SHAPE 8 X 8 S) mo
| 0xFD 2:Bu32 mo:Bmemop => VLOAD (SHAPE 8 X 8 U) mo
| 0xFD 3:Bu32 mo:Bmemop => VLOAD (SHAPE 16 X 4 S) mo
| 0xFD 4:Bu32 mo:Bmemop => VLOAD (SHAPE 16 X 4 U) mo
| 0xFD 5:Bu32 mo:Bmemop => VLOAD (SHAPE 32 X 2 S) mo
| 0xFD 6:Bu32 mo:Bmemop => VLOAD (SHAPE 32 X 2 U) mo
| 0xFD 7:Bu32 mo:Bmemop => VLOAD (SPLAT 8) mo
| 0xFD 8:Bu32 mo:Bmemop => VLOAD (SPLAT 16) mo
| 0xFD 9:Bu32 mo:Bmemop => VLOAD (SPLAT 32) mo
| 0xFD 10:Bu32 mo:Bmemop => VLOAD (SPLAT 64) mo
| 0xFD 92:Bu32 mo:Bmemop => VLOAD (ZERO 32) mo
| 0xFD 92:Bu32 mo:Bmemop => VLOAD (ZERO 64) mo
| 0xFD 11:Bu32 mo:Bmemop => VSTORE mo
| 0xFD 84:Bu32 mo:Bmemop l:Blaneidx => VLOAD_LANE 8 mo l
| 0xFD 85:Bu32 mo:Bmemop l:Blaneidx => VLOAD_LANE 16 mo l
| 0xFD 86:Bu32 mo:Bmemop l:Blaneidx => VLOAD_LANE 32 mo l
| 0xFD 87:Bu32 mo:Bmemop l:Blaneidx => VLOAD_LANE 64 mo l
| 0xFD 88:Bu32 mo:Bmemop l:Blaneidx => VSTORE_LANE 8 mo l
| 0xFD 89:Bu32 mo:Bmemop l:Blaneidx => VSTORE_LANE 16 mo l
| 0xFD 90:Bu32 mo:Bmemop l:Blaneidx => VSTORE_LANE 32 mo l
| 0xFD 91:Bu32 mo:Bmemop l:Blaneidx => VSTORE_LANE 64 mo l
| ...

grammar Binstr/vector-const : instr = ...
| 0xFD 12:Bu32 (b:Bbyte)^16 => VCONST V128 b' -- if $ibytes(128, b') = b
| ...

grammar Binstr/vector-shuffle : instr = ...
| 0xFD 13:Bu32 (l:Blaneidx)^16 => VSHUFFLE (I8 X 16) l
| ...

grammar Binstr/vector-lanes : instr = ...
| 0xFD 21:Bu32 l:Blaneidx => VEXTRACT_LANE (I8 X 16) S l
| 0xFD 22:Bu32 l:Blaneidx => VEXTRACT_LANE (I8 X 16) U l
| 0xFD 23:Bu32 l:Blaneidx => VREPLACE_LANE (I8 X 16) l
| 0xFD 24:Bu32 l:Blaneidx => VEXTRACT_LANE (I16 X 8) S l
| 0xFD 25:Bu32 l:Blaneidx => VEXTRACT_LANE (I16 X 8) U l
| 0xFD 26:Bu32 l:Blaneidx => VREPLACE_LANE (I16 X 8) l
| 0xFD 27:Bu32 l:Blaneidx => VEXTRACT_LANE (I32 X 4) l
| 0xFD 28:Bu32 l:Blaneidx => VREPLACE_LANE (I32 X 4) l
| 0xFD 29:Bu32 l:Blaneidx => VEXTRACT_LANE (I64 X 2) l
| 0xFD 30:Bu32 l:Blaneidx => VREPLACE_LANE (I64 X 2) l
| 0xFD 31:Bu32 l:Blaneidx => VEXTRACT_LANE (F32 X 4) l
| 0xFD 32:Bu32 l:Blaneidx => VREPLACE_LANE (F32 X 4) l
| 0xFD 33:Bu32 l:Blaneidx => VEXTRACT_LANE (F64 X 2) l
| 0xFD 34:Bu32 l:Blaneidx => VREPLACE_LANE (F64 X 2) l
| ...

grammar Binstr/vector-swizzle : instr = ...
| 0xFD 14:Bu32 => VSWIZZLE (I8 X 16)
| ...

grammar Binstr/vector-splat : instr = ...
| 0xFD 15:Bu32 => VSPLAT (I8 X 16)
| 0xFD 16:Bu32 => VSPLAT (I16 X 8)
| 0xFD 17:Bu32 => VSPLAT (I32 X 4)
| 0xFD 18:Bu32 => VSPLAT (I64 X 2)
| 0xFD 19:Bu32 => VSPLAT (F32 X 4)
| 0xFD 20:Bu32 => VSPLAT (F64 X 2)
| ...

grammar Binstr/vector-rel-i8x16 : instr = ...
| 0xFD 35:Bu32 => VRELOP (I8 X 16) EQ
| 0xFD 36:Bu32 => VRELOP (I8 X 16) NE
| 0xFD 37:Bu32 => VRELOP (I8 X 16) (LT S)
| 0xFD 38:Bu32 => VRELOP (I8 X 16) (LT U)
| 0xFD 39:Bu32 => VRELOP (I8 X 16) (GT S)
| 0xFD 40:Bu32 => VRELOP (I8 X 16) (GT U)
| 0xFD 41:Bu32 => VRELOP (I8 X 16) (LE S)
| 0xFD 42:Bu32 => VRELOP (I8 X 16) (LE U)
| 0xFD 43:Bu32 => VRELOP (I8 X 16) (GE S)
| 0xFD 44:Bu32 => VRELOP (I8 X 16) (GE U)
| ...

grammar Binstr/vector-rel-i16x8 : instr = ...
| 0xFD 45:Bu32 => VRELOP (I16 X 8) EQ
| 0xFD 46:Bu32 => VRELOP (I16 X 8) NE
| 0xFD 47:Bu32 => VRELOP (I16 X 8) (LT S)
| 0xFD 48:Bu32 => VRELOP (I16 X 8) (LT U)
| 0xFD 49:Bu32 => VRELOP (I16 X 8) (GT S)
| 0xFD 50:Bu32 => VRELOP (I16 X 8) (GT U)
| 0xFD 51:Bu32 => VRELOP (I16 X 8) (LE S)
| 0xFD 52:Bu32 => VRELOP (I16 X 8) (LE U)
| 0xFD 53:Bu32 => VRELOP (I16 X 8) (GE S)
| 0xFD 54:Bu32 => VRELOP (I16 X 8) (GE U)
| ...

grammar Binstr/vector-rel-i32x4 : instr = ...
| 0xFD 55:Bu32 => VRELOP (I32 X 4) EQ
| 0xFD 56:Bu32 => VRELOP (I32 X 4) NE
| 0xFD 57:Bu32 => VRELOP (I32 X 4) (LT S)
| 0xFD 58:Bu32 => VRELOP (I32 X 4) (LT U)
| 0xFD 59:Bu32 => VRELOP (I32 X 4) (GT S)
| 0xFD 60:Bu32 => VRELOP (I32 X 4) (GT U)
| 0xFD 61:Bu32 => VRELOP (I32 X 4) (LE S)
| 0xFD 62:Bu32 => VRELOP (I32 X 4) (LE U)
| 0xFD 63:Bu32 => VRELOP (I32 X 4) (GE S)
| 0xFD 64:Bu32 => VRELOP (I32 X 4) (GE U)
| ...

grammar Binstr/vector-rel-i64x2 : instr = ...
| 0xFD 214:Bu32 => VRELOP (I64 X 2) EQ
| 0xFD 215:Bu32 => VRELOP (I64 X 2) NE
| 0xFD 216:Bu32 => VRELOP (I64 X 2) (LT S)
| 0xFD 217:Bu32 => VRELOP (I64 X 2) (GT S)
| 0xFD 218:Bu32 => VRELOP (I64 X 2) (LE S)
| 0xFD 219:Bu32 => VRELOP (I64 X 2) (GE S)
| ...

grammar Binstr/vector-rel-f32x4 : instr = ...
| 0xFD 65:Bu32 => VRELOP (F32 X 4) EQ
| 0xFD 66:Bu32 => VRELOP (F32 X 4) NE
| 0xFD 67:Bu32 => VRELOP (F32 X 4) LT
| 0xFD 68:Bu32 => VRELOP (F32 X 4) GT
| 0xFD 69:Bu32 => VRELOP (F32 X 4) LE
| 0xFD 70:Bu32 => VRELOP (F32 X 4) GE
| ...

grammar Binstr/vector-rel-f64x2 : instr = ...
| 0xFD 71:Bu32 => VRELOP (F64 X 2) EQ
| 0xFD 72:Bu32 => VRELOP (F64 X 2) NE
| 0xFD 73:Bu32 => VRELOP (F64 X 2) LT
| 0xFD 74:Bu32 => VRELOP (F64 X 2) GT
| 0xFD 75:Bu32 => VRELOP (F64 X 2) LE
| 0xFD 76:Bu32 => VRELOP (F64 X 2) GE
| ...

grammar Binstr/vector-vv : instr = ...
| 0xFD 77:Bu32 => VVUNOP V128 NOT
| 0xFD 78:Bu32 => VVBINOP V128 AND
| 0xFD 79:Bu32 => VVBINOP V128 ANDNOT
| 0xFD 80:Bu32 => VVBINOP V128 OR
| 0xFD 81:Bu32 => VVBINOP V128 XOR
| 0xFD 82:Bu32 => VVTERNOP V128 BITSELECT
| 0xFD 83:Bu32 => VVTESTOP V128 ANY_TRUE
| ...

grammar Binstr/vector-v-i8x16 : instr = ...
| 0xFD 96:Bu32 => VUNOP (I8 X 16) ABS
| 0xFD 97:Bu32 => VUNOP (I8 X 16) NEG
| 0xFD 98:Bu32 => VUNOP (I8 X 16) POPCNT
| 0xFD 99:Bu32 => VTESTOP (I8 X 16) ALL_TRUE
| 0xFD 100:Bu32 => VBITMASK (I8 X 16)
| 0xFD 101:Bu32 => VNARROW (I8 X 16) (I16 X 8) S
| 0xFD 102:Bu32 => VNARROW (I8 X 16) (I16 X 8) U
| 0xFD 107:Bu32 => VSHIFTOP (I8 X 16) SHL
| 0xFD 108:Bu32 => VSHIFTOP (I8 X 16) (SHR S)
| 0xFD 109:Bu32 => VSHIFTOP (I8 X 16) (SHR U)
| 0xFD 110:Bu32 => VBINOP (I8 X 16) ADD
| 0xFD 111:Bu32 => VBINOP (I8 X 16) (ADD_SAT S)
| 0xFD 112:Bu32 => VBINOP (I8 X 16) (ADD_SAT U)
| 0xFD 113:Bu32 => VBINOP (I8 X 16) SUB
| 0xFD 114:Bu32 => VBINOP (I8 X 16) (SUB_SAT S)
| 0xFD 115:Bu32 => VBINOP (I8 X 16) (SUB_SAT U)
| 0xFD 118:Bu32 => VBINOP (I8 X 16) (MIN S)
| 0xFD 119:Bu32 => VBINOP (I8 X 16) (MIN U)
| 0xFD 120:Bu32 => VBINOP (I8 X 16) (MAX S)
| 0xFD 121:Bu32 => VBINOP (I8 X 16) (MAX U)
| 0xFD 123:Bu32 => VBINOP (I8 X 16) AVGR_U
| ...

grammar Binstr/vector-v-i16x8 : instr = ...
| 0xFD 124:Bu32 => VEXTUNOP (I16 X 8) (I8 X 16) EXTADD_PAIRWISE S
| 0xFD 125:Bu32 => VEXTUNOP (I16 X 8) (I8 X 16) EXTADD_PAIRWISE U
| 0xFD 128:Bu32 => VUNOP (I16 X 8) ABS
| 0xFD 129:Bu32 => VUNOP (I16 X 8) NEG
| 0xFD 130:Bu32 => VBINOP (I16 X 8) Q15MULR_SAT_S
| 0xFD 131:Bu32 => VTESTOP (I16 X 8) ALL_TRUE
| 0xFD 132:Bu32 => VBITMASK (I16 X 8)
| 0xFD 133:Bu32 => VNARROW (I16 X 8) (I32 X 4) S
| 0xFD 134:Bu32 => VNARROW (I16 X 8) (I32 X 4) U
| 0xFD 135:Bu32 => VCVTOP (I16 X 8) EXTEND LOW (I8 X 16) S
| 0xFD 136:Bu32 => VCVTOP (I16 X 8) EXTEND HIGH (I8 X 16) S
| 0xFD 137:Bu32 => VCVTOP (I16 X 8) EXTEND LOW (I8 X 16) U
| 0xFD 138:Bu32 => VCVTOP (I16 X 8) EXTEND HIGH (I8 X 16) U
| 0xFD 139:Bu32 => VSHIFTOP (I16 X 8) SHL
| 0xFD 140:Bu32 => VSHIFTOP (I16 X 8) (SHR S)
| 0xFD 141:Bu32 => VSHIFTOP (I16 X 8) (SHR U)
| 0xFD 142:Bu32 => VBINOP (I16 X 8) ADD
| 0xFD 143:Bu32 => VBINOP (I16 X 8) (ADD_SAT S)
| 0xFD 144:Bu32 => VBINOP (I16 X 8) (ADD_SAT U)
| 0xFD 145:Bu32 => VBINOP (I16 X 8) SUB
| 0xFD 146:Bu32 => VBINOP (I16 X 8) (SUB_SAT S)
| 0xFD 147:Bu32 => VBINOP (I16 X 8) (SUB_SAT U)
| 0xFD 149:Bu32 => VBINOP (I16 X 8) MUL
| 0xFD 150:Bu32 => VBINOP (I16 X 8) (MIN S)
| 0xFD 151:Bu32 => VBINOP (I16 X 8) (MIN U)
| 0xFD 152:Bu32 => VBINOP (I16 X 8) (MAX S)
| 0xFD 153:Bu32 => VBINOP (I16 X 8) (MAX U)
| 0xFD 155:Bu32 => VBINOP (I16 X 8) AVGR_U
| 0xFD 156:Bu32 => VEXTBINOP (I16 X 8) (I8 X 16) (EXTMUL LOW) S
| 0xFD 157:Bu32 => VEXTBINOP (I16 X 8) (I8 X 16) (EXTMUL HIGH) S
| 0xFD 158:Bu32 => VEXTBINOP (I16 X 8) (I8 X 16) (EXTMUL LOW) U
| 0xFD 159:Bu32 => VEXTBINOP (I16 X 8) (I8 X 16) (EXTMUL HIGH) U
| ...

grammar Binstr/vector-v-i32x4 : instr = ...
| 0xFD 126:Bu32 => VEXTUNOP (I32 X 4) (I16 X 8) EXTADD_PAIRWISE S
| 0xFD 127:Bu32 => VEXTUNOP (I32 X 4) (I16 X 8) EXTADD_PAIRWISE U
| 0xFD 160:Bu32 => VUNOP (I32 X 4) ABS
| 0xFD 161:Bu32 => VUNOP (I32 X 4) NEG
| 0xFD 163:Bu32 => VTESTOP (I32 X 4) ALL_TRUE
| 0xFD 164:Bu32 => VBITMASK (I32 X 4)
| 0xFD 167:Bu32 => VCVTOP (I32 X 4) EXTEND LOW (I16 X 8) S
| 0xFD 168:Bu32 => VCVTOP (I32 X 4) EXTEND HIGH (I16 X 8) S
| 0xFD 169:Bu32 => VCVTOP (I32 X 4) EXTEND LOW (I16 X 8) U
| 0xFD 170:Bu32 => VCVTOP (I32 X 4) EXTEND HIGH (I16 X 8) U
| 0xFD 171:Bu32 => VSHIFTOP (I32 X 4) SHL
| 0xFD 172:Bu32 => VSHIFTOP (I32 X 4) (SHR S)
| 0xFD 173:Bu32 => VSHIFTOP (I32 X 4) (SHR U)
| 0xFD 174:Bu32 => VBINOP (I32 X 4) ADD
| 0xFD 177:Bu32 => VBINOP (I32 X 4) SUB
| 0xFD 181:Bu32 => VBINOP (I32 X 4) MUL
| 0xFD 182:Bu32 => VBINOP (I32 X 4) (MIN S)
| 0xFD 183:Bu32 => VBINOP (I32 X 4) (MIN U)
| 0xFD 184:Bu32 => VBINOP (I32 X 4) (MAX S)
| 0xFD 185:Bu32 => VBINOP (I32 X 4) (MAX U)
| 0xFD 186:Bu32 => VEXTBINOP (I32 X 4) (I16 X 8) DOT S
| 0xFD 188:Bu32 => VEXTBINOP (I32 X 4) (I16 X 8) (EXTMUL LOW) S
| 0xFD 189:Bu32 => VEXTBINOP (I32 X 4) (I16 X 8) (EXTMUL HIGH) S
| 0xFD 190:Bu32 => VEXTBINOP (I32 X 4) (I16 X 8) (EXTMUL LOW) U
| 0xFD 191:Bu32 => VEXTBINOP (I32 X 4) (I16 X 8) (EXTMUL HIGH) U
| ...

grammar Binstr/vector-v-i64x2 : instr = ...
| 0xFD 192:Bu32 => VUNOP (I64 X 2) ABS
| 0xFD 193:Bu32 => VUNOP (I64 X 2) NEG
| 0xFD 195:Bu32 => VTESTOP (I64 X 2) ALL_TRUE
| 0xFD 196:Bu32 => VBITMASK (I64 X 2)
| 0xFD 199:Bu32 => VCVTOP (I64 X 2) EXTEND LOW (I32 X 4) S
| 0xFD 200:Bu32 => VCVTOP (I64 X 2) EXTEND HIGH (I32 X 4) S
| 0xFD 201:Bu32 => VCVTOP (I64 X 2) EXTEND LOW (I32 X 4) U
| 0xFD 202:Bu32 => VCVTOP (I64 X 2) EXTEND HIGH (I32 X 4) U
| 0xFD 203:Bu32 => VSHIFTOP (I64 X 2) SHL
| 0xFD 204:Bu32 => VSHIFTOP (I64 X 2) (SHR S)
| 0xFD 205:Bu32 => VSHIFTOP (I64 X 2) (SHR U)
| 0xFD 206:Bu32 => VBINOP (I64 X 2) ADD
| 0xFD 209:Bu32 => VBINOP (I64 X 2) SUB
| 0xFD 213:Bu32 => VBINOP (I64 X 2) MUL
| 0xFD 220:Bu32 => VEXTBINOP (I64 X 2) (I32 X 4) (EXTMUL LOW) S
| 0xFD 221:Bu32 => VEXTBINOP (I64 X 2) (I32 X 4) (EXTMUL HIGH) S
| 0xFD 222:Bu32 => VEXTBINOP (I64 X 2) (I32 X 4) (EXTMUL LOW) U
| 0xFD 223:Bu32 => VEXTBINOP (I64 X 2) (I32 X 4) (EXTMUL HIGH) U
| ...

grammar Binstr/vector-v-f32x4 : instr = ...
| 0xFD 103:Bu32 => VUNOP (F32 X 4) CEIL
| 0xFD 104:Bu32 => VUNOP (F32 X 4) FLOOR
| 0xFD 105:Bu32 => VUNOP (F32 X 4) TRUNC
| 0xFD 106:Bu32 => VUNOP (F32 X 4) NEAREST
| 0xFD 224:Bu32 => VUNOP (F32 X 4) ABS
| 0xFD 225:Bu32 => VUNOP (F32 X 4) NEG
| 0xFD 227:Bu32 => VUNOP (F32 X 4) SQRT
| 0xFD 228:Bu32 => VBINOP (F32 X 4) ADD
| 0xFD 229:Bu32 => VBINOP (F32 X 4) SUB
| 0xFD 230:Bu32 => VBINOP (F32 X 4) MUL
| 0xFD 231:Bu32 => VBINOP (F32 X 4) DIV
| 0xFD 232:Bu32 => VBINOP (F32 X 4) MIN
| 0xFD 233:Bu32 => VBINOP (F32 X 4) MAX
| 0xFD 234:Bu32 => VBINOP (F32 X 4) PMIN
| 0xFD 235:Bu32 => VBINOP (F32 X 4) PMAX
| ...

grammar Binstr/vector-v-f64x2 : instr = ...
| 0xFD 116:Bu32 => VUNOP (F64 X 2) CEIL
| 0xFD 117:Bu32 => VUNOP (F64 X 2) FLOOR
| 0xFD 122:Bu32 => VUNOP (F64 X 2) TRUNC
| 0xFD 148:Bu32 => VUNOP (F64 X 2) NEAREST
| 0xFD 236:Bu32 => VUNOP (F64 X 2) ABS
| 0xFD 237:Bu32 => VUNOP (F64 X 2) NEG
| 0xFD 239:Bu32 => VUNOP (F64 X 2) SQRT
| 0xFD 240:Bu32 => VBINOP (F64 X 2) ADD
| 0xFD 241:Bu32 => VBINOP (F64 X 2) SUB
| 0xFD 242:Bu32 => VBINOP (F64 X 2) MUL
| 0xFD 243:Bu32 => VBINOP (F64 X 2) DIV
| 0xFD 244:Bu32 => VBINOP (F64 X 2) MIN
| 0xFD 245:Bu32 => VBINOP (F64 X 2) MAX
| 0xFD 246:Bu32 => VBINOP (F64 X 2) PMIN
| 0xFD 247:Bu32 => VBINOP (F64 X 2) PMAX
| ...

grammar Binstr/vector-cvt : instr = ...
| 0xFD 248:Bu32 => VCVTOP (I32 X 4) TRUNC_SAT (F32 X 4) S
| 0xFD 249:Bu32 => VCVTOP (I32 X 4) TRUNC_SAT (F32 X 4) U
| 0xFD 250:Bu32 => VCVTOP (F32 X 4) CONVERT (I32 X 4) S
| 0xFD 251:Bu32 => VCVTOP (F32 X 4) CONVERT (I32 X 4) U
| 0xFD 252:Bu32 => VCVTOP (I32 X 4) TRUNC_SAT (F64 X 2) S ZERO
| 0xFD 253:Bu32 => VCVTOP (I32 X 4) TRUNC_SAT (F64 X 2) U ZERO
| 0xFD 254:Bu32 => VCVTOP (F64 X 2) CONVERT LOW (I32 X 4) S
| 0xFD 255:Bu32 => VCVTOP (F64 X 2) CONVERT LOW (I32 X 4) U
| 0xFD 94:Bu32 => VCVTOP (F32 X 4) DEMOTE (F64 X 2) ZERO
| 0xFD 95:Bu32 => VCVTOP (F64 X 2) PROMOTE LOW (F32 X 4)
| ...


;; Expressions

grammar Bexpr : expr =
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