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Make shimDMAAllocation have DeviceOp as parent (#556)
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@fifield
fifield authored Jul 26, 2023
1 parent 5c241b3 commit 0480134
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Showing 15 changed files with 43 additions and 39 deletions.
2 changes: 1 addition & 1 deletion include/aie/Dialect/AIE/IR/AIE.td
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Expand Up @@ -1279,7 +1279,7 @@ def AIE_PutCascadeOp: AIE_Op<"putCascade", [HasParent<"CoreOp">]> {
let assemblyFormat = [{ `(` $cascadeValue `:` type($cascadeValue) `)` attr-dict }];
}

def AIE_ShimDMAAllocationOp : AIE_Op<"shimDMAAllocation", [HasParent<"ModuleOp">]> {
def AIE_ShimDMAAllocationOp : AIE_Op<"shimDMAAllocation", [HasParent<"DeviceOp">]> {
let summary = "Runtime allocation information for a single shim DMA";
let description = [{
This op exists for cases where shimDMA configuration is performed outside of MLIR-AIE
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6 changes: 3 additions & 3 deletions lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp
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Expand Up @@ -1108,7 +1108,7 @@ struct AIEObjectFifoStatefulTransformPass
}

/// Function used to generate, from an objectFifo with a shimTile endpoint, a
/// shimDMAAllocationInfoOp containing the channelDir, channelIndex and
/// shimDMAAllocationOp containing the channelDir, channelIndex and
/// shimTile col assigned by the objectFifo lowering.
void createObjectFifoAllocationInfo(OpBuilder &builder, MLIRContext *ctx,
StringRef name, int colIndex,
Expand Down Expand Up @@ -1240,7 +1240,7 @@ struct AIEObjectFifoStatefulTransformPass
createDMA(device, builder, producer, producerChan.first,
producerChan.second, 0);
// generate objectFifo allocation info
builder.setInsertionPointAfter(device);
builder.setInsertionPoint(&device.getBody()->back());
if (producer.getProducerTileOp().isShimTile())
createObjectFifoAllocationInfo(builder, ctx,
producer.name()->getValue(),
Expand All @@ -1254,7 +1254,7 @@ struct AIEObjectFifoStatefulTransformPass
createDMA(device, builder, consumer, consumerChan.first,
consumerChan.second, 1);
// generate objectFifo allocation info
builder.setInsertionPointAfter(device);
builder.setInsertionPoint(&device.getBody()->back());
if (consumer.getProducerTileOp().isShimTile())
createObjectFifoAllocationInfo(
builder, ctx, producer.name()->getValue(),
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34 changes: 18 additions & 16 deletions lib/Targets/AIETargets.cpp
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Expand Up @@ -180,23 +180,25 @@ void registerAIETranslations() {
TranslateFromMLIRRegistration registrationShimDMAToJSON(
"aie-generate-json", "Transform AIE shim DMA allocation info into JSON",
[](ModuleOp module, raw_ostream &output) {
llvm::json::Object moduleJSON;
for (auto shimDMA_meta : module.getOps<ShimDMAAllocationOp>()) {
llvm::json::Object shimJSON;
auto channelDir = shimDMA_meta.getChannelDirAttr();
shimJSON["channelDir"] = attrToJSON(channelDir);
auto channelIndex = shimDMA_meta.getChannelIndexAttr();
shimJSON["channelIndex"] = attrToJSON(channelIndex);
auto col = shimDMA_meta.getColAttr();
shimJSON["col"] = attrToJSON(col);
moduleJSON[shimDMA_meta.getSymName()] =
llvm::json::Value(std::move(shimJSON));
for (auto d : module.getOps<DeviceOp>()) {
llvm::json::Object moduleJSON;
for (auto shimDMA_meta : d.getOps<ShimDMAAllocationOp>()) {
llvm::json::Object shimJSON;
auto channelDir = shimDMA_meta.getChannelDirAttr();
shimJSON["channelDir"] = attrToJSON(channelDir);
auto channelIndex = shimDMA_meta.getChannelIndexAttr();
shimJSON["channelIndex"] = attrToJSON(channelIndex);
auto col = shimDMA_meta.getColAttr();
shimJSON["col"] = attrToJSON(col);
moduleJSON[shimDMA_meta.getSymName()] =
llvm::json::Value(std::move(shimJSON));
}
llvm::json::Value topv(std::move(moduleJSON));
std::string ret;
llvm::raw_string_ostream ss(ret);
ss << llvm::formatv("{0:2}", topv) << "\n";
output << ss.str();
}
llvm::json::Value topv(std::move(moduleJSON));
std::string ret;
llvm::raw_string_ostream ss(ret);
ss << llvm::formatv("{0:2}", topv) << "\n";
output << ss.str();
return success();
},
registerDialects);
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10 changes: 6 additions & 4 deletions test/Targets/AIEGenerateJSON/shim_alloc.mlir
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Expand Up @@ -36,8 +36,10 @@
// CHECK: }

module @alloc {
AIE.shimDMAAllocation("of_out_1", S2MM, 1, 2)
AIE.shimDMAAllocation("of_in_1", MM2S, 1, 2)
AIE.shimDMAAllocation("of_out_0", S2MM, 0, 2)
AIE.shimDMAAllocation("of_in_0", MM2S, 0, 2)
AIE.device(xcve2302) {
AIE.shimDMAAllocation("of_out_1", S2MM, 1, 2)
AIE.shimDMAAllocation("of_in_1", MM2S, 1, 2)
AIE.shimDMAAllocation("of_out_0", S2MM, 0, 2)
AIE.shimDMAAllocation("of_in_0", MM2S, 0, 2)
}
}
8 changes: 4 additions & 4 deletions test/objectFifo-stateful-transform/allocation_info_test.mlir
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Expand Up @@ -21,11 +21,11 @@
// CHECK: AIE.flow({{.*}}, DMA : {{.*}}, {{.*}}, DMA : {{.*}})
// CHECK: AIE.flow({{.*}}, DMA : {{.*}}, {{.*}}, DMA : {{.*}})
// CHECK: AIE.flow({{.*}}, DMA : {{.*}}, {{.*}}, DMA : {{.*}})
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: }
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: AIE.shimDMAAllocation({{.*}}, {{.*}}, {{.*}}, 2)
// CHECK: }

module @alloc {
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2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/link_test_AIE1.mlir
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Expand Up @@ -29,6 +29,7 @@
// CHECK: %10 = AIE.lock(%2, 0) {init = 0 : i32, sym_name = "link2_cons_lock_0"}
// CHECK: %11 = AIE.lock(%2, 1) {init = 0 : i32, sym_name = "link2_cons_lock_1"}
// CHECK: %12 = AIE.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32>
// CHECK: AIE.shimDMAAllocation("link1", MM2S, 0, 2)
// CHECK: %13 = AIE.shimDMA(%0) {
// CHECK: %16 = AIE.dmaStart(MM2S, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand Down Expand Up @@ -82,7 +83,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("link1", MM2S, 0, 2)
// CHECK: }

module @link_AIE1 {
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2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/link_test_DDR_to_L1.mlir
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Expand Up @@ -30,6 +30,7 @@
// CHECK: %11 = AIE.lock(%2, 0) {init = 2 : i32, sym_name = "from_memTile_cons_prod_lock"}
// CHECK: %12 = AIE.lock(%2, 1) {init = 0 : i32, sym_name = "from_memTile_cons_cons_lock"}
// CHECK: %13 = AIE.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32>
// CHECK: AIE.shimDMAAllocation("to_memTile", MM2S, 0, 2)
// CHECK: %14 = AIE.shimDMA(%0) {
// CHECK: %17 = AIE.dmaStart(MM2S, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand Down Expand Up @@ -83,7 +84,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("to_memTile", MM2S, 0, 2)
// CHECK: }

module @link_DDR_L1 {
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2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/link_test_L1_to_DDR.mlir
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Expand Up @@ -72,6 +72,7 @@
// CHECK: ^bb6: // pred: ^bb3
// CHECK: AIE.end
// CHECK: }
// CHECK: AIE.shimDMAAllocation("from_memTile", S2MM, 0, 2)
// CHECK: %16 = AIE.shimDMA(%0) {
// CHECK: %17 = AIE.dmaStart(S2MM, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand All @@ -83,7 +84,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("from_memTile", S2MM, 0, 2)
// CHECK: }

module @link_L1_DDR {
Expand Down
2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/link_test_broadcast.mlir
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Expand Up @@ -45,6 +45,7 @@
// CHECK: %24 = AIE.buffer(%3) {sym_name = "skip_connection_cons_buff_1"} : memref<16xi32>
// CHECK: %25 = AIE.lock(%3, 2) {init = 2 : i32, sym_name = "skip_connection_cons_prod_lock"}
// CHECK: %26 = AIE.lock(%3, 3) {init = 0 : i32, sym_name = "skip_connection_cons_cons_lock"}
// CHECK: AIE.shimDMAAllocation("link1", MM2S, 0, 2)
// CHECK: %27 = AIE.memTileDMA(%1) {
// CHECK: %30 = AIE.dmaStart(S2MM, 0, ^bb1, ^bb3)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2
Expand Down Expand Up @@ -132,7 +133,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("link1", MM2S, 0, 2)
// CHECK: }

module @link_broadcast {
Expand Down
2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/link_test_distribute.mlir
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Expand Up @@ -42,6 +42,7 @@
// CHECK: %21 = AIE.lock(%4, 0) {init = 2 : i32, sym_name = "link4_cons_prod_lock"}
// CHECK: %22 = AIE.lock(%4, 1) {init = 0 : i32, sym_name = "link4_cons_cons_lock"}
// CHECK: %23 = AIE.external_buffer {sym_name = "ext_buffer_in"} : memref<48xi32>
// CHECK: AIE.shimDMAAllocation("link1", MM2S, 0, 2)
// CHECK: %24 = AIE.shimDMA(%0) {
// CHECK: %29 = AIE.dmaStart(MM2S, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand Down Expand Up @@ -149,7 +150,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("link1", MM2S, 0, 2)
// CHECK: }

module @link_distribute {
Expand Down
2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/link_test_join.mlir
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Expand Up @@ -171,6 +171,7 @@
// CHECK: ^bb3: // pred: ^bb0
// CHECK: AIE.end
// CHECK: }
// CHECK: AIE.shimDMAAllocation("link5", S2MM, 0, 2)
// CHECK: %34 = AIE.shimDMA(%0) {
// CHECK: %35 = AIE.dmaStart(S2MM, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand All @@ -182,7 +183,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("link5", S2MM, 0, 2)
// CHECK: }

module @link_join {
Expand Down
2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/register_external_buffers_test.mlir
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Expand Up @@ -39,6 +39,7 @@
// CHECK: AIE.useLock(%6, Release, 0)
// CHECK: AIE.end
// CHECK: }
// CHECK: AIE.shimDMAAllocation("ext_of", MM2S, 0, 7)
// CHECK: %11 = AIE.shimDMA(%1) {
// CHECK: %13 = AIE.dmaStart(MM2S, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand Down Expand Up @@ -70,7 +71,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("ext_of", MM2S, 0, 7)
// CHECK: }

module @register_external_buffers {
Expand Down
2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/shimRow_mem_test.mlir
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Expand Up @@ -39,6 +39,7 @@
// CHECK: AIE.useLock(%6, Release, 0)
// CHECK: AIE.end
// CHECK: }
// CHECK: AIE.shimDMAAllocation("objfifo", MM2S, 0, 7)
// CHECK: %11 = AIE.shimDMA(%1) {
// CHECK: %13 = AIE.dmaStart(MM2S, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand Down Expand Up @@ -70,7 +71,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("objfifo", MM2S, 0, 7)
// CHECK: }

module @shimRow_mem {
Expand Down
4 changes: 2 additions & 2 deletions test/objectFifo-stateful-transform/shim_AIE2_test.mlir
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Expand Up @@ -32,6 +32,7 @@
// CHECK: %13 = AIE.lock(%1, 3) {init = 0 : i32, sym_name = "of_out_cons_cons_lock"}
// CHECK: %14 = AIE.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32>
// CHECK: %15 = AIE.external_buffer {sym_name = "ext_buffer_out"} : memref<64xi32>
// CHECK: AIE.shimDMAAllocation("of_in", MM2S, 0, 2)
// CHECK: %16 = AIE.shimDMA(%1) {
// CHECK: %18 = AIE.dmaStart(MM2S, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand All @@ -49,6 +50,7 @@
// CHECK: ^bb4: // pred: ^bb2
// CHECK: AIE.end
// CHECK: }
// CHECK: AIE.shimDMAAllocation("of_out", S2MM, 0, 2)
// CHECK: %17 = AIE.mem(%0) {
// CHECK: %18 = AIE.dmaStart(S2MM, 0, ^bb1, ^bb3)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2
Expand Down Expand Up @@ -77,8 +79,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("of_out", S2MM, 0, 2)
// CHECK: AIE.shimDMAAllocation("of_in", MM2S, 0, 2)
// CHECK: }

module @shim_AIE2 {
Expand Down
2 changes: 1 addition & 1 deletion test/objectFifo-stateful-transform/shim_broadcast_test.mlir
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Expand Up @@ -36,6 +36,7 @@
// CHECK: %16 = AIE.lock(%1, 0) {init = 2 : i32, sym_name = "of_in_0_cons_prod_lock"}
// CHECK: %17 = AIE.lock(%1, 1) {init = 0 : i32, sym_name = "of_in_0_cons_cons_lock"}
// CHECK: %18 = AIE.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32>
// CHECK: AIE.shimDMAAllocation("of_in", MM2S, 0, 2)
// CHECK: %19 = AIE.shimDMA(%0) {
// CHECK: %23 = AIE.dmaStart(MM2S, 0, ^bb1, ^bb2)
// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1
Expand Down Expand Up @@ -92,7 +93,6 @@
// CHECK: AIE.end
// CHECK: }
// CHECK: }
// CHECK: AIE.shimDMAAllocation("of_in", MM2S, 0, 2)
// CHECK: }

module @shim_broadcast {
Expand Down

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