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Add more DMA tests
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@stephenneuendorffer
stephenneuendorffer committed Aug 5, 2023
1 parent 5a4a31c commit 109566c
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65 changes: 65 additions & 0 deletions test/Targets/AIEGenerateXAIE/aie2_tileDMA_locks.mlir
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//===- aie2_tileDMA.mlir ---------------------------------------*- MLIR -*-===//
//
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023 Advanced Micro Devices, Inc.
//
//===----------------------------------------------------------------------===//

// RUN: aie-translate --aie-generate-xaie %s | FileCheck %s

// CHECK: XAie_DmaDesc [[bd0:.*]];
// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,4))
// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit(4,1))
// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)
// CHECK: XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 1, /* enableNextBd */ 1)
// CHECK: XAie_DmaEnableBd(&([[bd0]]))
// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,4), /* bd */ 0)
// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(7,4), /* ChNum */0, /* dmaDir */ DMA_S2MM, /* BdNum */0)
// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(7,4), /* ChNum */ 0, /* dmaDir */ DMA_S2MM)

module @aie_module {
AIE.device(xcve2802) {
%t63 = AIE.tile(6, 4)
%t73 = AIE.tile(7, 4)
%t72 = AIE.tile(7, 3)
%t74 = AIE.tile(7, 5)

%buf_e = AIE.buffer(%t63) {address = 0 : i32, sym_name = "east" } : memref<256xi32>
%buf_l = AIE.buffer(%t73) {address = 1824 : i32, sym_name = "local" } : memref<256xi32>
%buf_n = AIE.buffer(%t74) {address = 0 : i32, sym_name = "north" } : memref<256xi32>
%buf_s = AIE.buffer(%t72) {address = 0 : i32, sym_name = "south" } : memref<256xi32>

%lock_e = AIE.lock(%t63, 0)
%lock_l1 = AIE.lock(%t73, 3)
%lock_l2 = AIE.lock(%t73, 4)
%lock_n = AIE.lock(%t74, 0)
%lock_s = AIE.lock(%t72, 0)

// Tile DMA
%m73 = AIE.mem(%t73) {
%srcDma = AIE.dmaStart("S2MM", 0, ^bd0, ^end)
^bd0:
AIE.useLock(%lock_l1, AcquireGreaterEqual, 1)
AIE.dmaBd(<%buf_l : memref<256xi32>, 0, 256>, 0)
AIE.useLock(%lock_l2, Release, 1)
AIE.nextBd ^bd1
^bd1:
AIE.dmaBd(<%buf_l : memref<256xi32>, 0, 256>, 0)
AIE.useLock(%lock_l1, Release, 1)
AIE.nextBd ^bd2
^bd2:
AIE.dmaBd(<%buf_l : memref<256xi32>, 0, 256>, 0)
AIE.useLock(%lock_l1, Release, 1)
AIE.nextBd ^bd3
^bd3:
AIE.dmaBd(<%buf_l : memref<256xi32>, 0, 256>, 0)
AIE.useLock(%lock_l1, Release, 1)
AIE.nextBd ^end
^end:
AIE.end
}
}
}
71 changes: 71 additions & 0 deletions test/Targets/AIEGenerateXAIE/memTileDMA2.mlir
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//===- memTileDMA.mlir ------------------------------------------*- MLIR -*-===//
//
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023 Advanced Micro Devices, Inc.
//
//===----------------------------------------------------------------------===//

// RUN: aie-translate --aie-generate-xaie %s | FileCheck %s

// CHECK: XAie_DmaDesc [[bd0:.*]];
// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1))
// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1))
// CHECK: [[bd0]].LockDesc.LockAcqEn = XAIE_DISABLE;
// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x0, /* len */ 16 * 4)
// CHECK: XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 1, /* enableNextBd */ 1)
// CHECK: XAie_DmaEnableBd(&([[bd0]]))
// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1), /* bd */ 0)

// CHECK: XAie_DmaDesc [[bd1:.*]];
// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1))
// CHECK: XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(0,0),XAie_LockInit(64,1))
// CHECK: [[bd1]].LockDesc.LockAcqEn = XAIE_DISABLE;
// CHECK: XAie_DmaSetAddrLen(&([[bd1]]), /* addrA */ 0x80000, /* len */ 16 * 4)
// CHECK: XAie_DmaSetNextBd(&([[bd1]]), /* nextbd */ 2, /* enableNextBd */ 1)
// CHECK: XAie_DmaEnableBd(&([[bd1]]))
// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1), /* bd */ 1)

// CHECK: XAie_DmaDesc [[bd2:.*]];
// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd2]]), XAie_TileLoc(2,1))
// CHECK: XAie_DmaSetLock(&([[bd2]]), XAie_LockInit(0,0),XAie_LockInit(128,1))
// CHECK: [[bd2]].LockDesc.LockAcqEn = XAIE_DISABLE;
// CHECK: XAie_DmaSetAddrLen(&([[bd2]]), /* addrA */ 0x100000, /* len */ 16 * 4)
// CHECK: XAie_DmaSetNextBd(&([[bd2]]), /* nextbd */ 0, /* enableNextBd */ 0)
// CHECK: XAie_DmaEnableBd(&([[bd2]]))
// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd2]]), XAie_TileLoc(2,1), /* bd */ 2)

module @aie_module {
AIE.device(xcve2802) {
%t00 = AIE.tile(1, 1)
%t01 = AIE.tile(2, 1)
%t02 = AIE.tile(3, 1)
%buf_w = AIE.buffer(%t00) { address = 0 : i32, sym_name = "west" } : memref<16xi32>
%buf_l = AIE.buffer(%t01) { address = 0 : i32, sym_name = "local" } : memref<16xi32>
%buf_e = AIE.buffer(%t02) { address = 0 : i32, sym_name = "east" } : memref<16xi32>

%lock_w = AIE.lock(%t00, 0)
%lock_l = AIE.lock(%t01, 0)
%lock_e = AIE.lock(%t02, 0)

%m01 = AIE.memTileDMA(%t01) {
%srcDma = AIE.dmaStart(S2MM, 0, ^bd0, ^end)
^bd0:
AIE.dmaBd(<%buf_w : memref<16xi32>, 0, 16>, 0)
AIE.useLock(%lock_w, "Release", 1)
AIE.nextBd ^bd1
^bd1:
AIE.dmaBd(<%buf_l : memref<16xi32>, 0, 16>, 0)
AIE.useLock(%lock_l, "Release", 1)
AIE.nextBd ^bd2
^bd2:
AIE.dmaBd(<%buf_e : memref<16xi32>, 0, 16>, 0)
AIE.useLock(%lock_e, "Release", 1)
AIE.nextBd ^end
^end:
AIE.end
}
}
}

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