more rename ipu->npu

include/aie/Dialect/AIE/IR/AIEAttrs.td

@@ -100,7 +100,7 @@ def AIEDevice: I32EnumAttr<"AIEDevice", "AIE Device",
     I32EnumAttrCase<"xcvc1902", 1>,
     I32EnumAttrCase<"xcve2302", 2>,
     I32EnumAttrCase<"xcve2802", 3>,
-    I32EnumAttrCase<"ipu", 4>
+    I32EnumAttrCase<"npu", 4>
   ]> {
 
   let cppNamespace = "xilinx::AIE";

include/aie/Dialect/AIEX/IR/AIEX.td

@@ -463,7 +463,7 @@ def AIE_SelectOp: AIEX_Op<"select", []>, Results<(outs Index)> {
   ];
 }
 
-def AIE_NpuDmaMemcpyNdOp: AIEX_Op<"ipu.dma_memcpy_nd", [
+def AIE_NpuDmaMemcpyNdOp: AIEX_Op<"npu.dma_memcpy_nd", [
     AttrSizedOperandSegments,
     MyOffsetSizeAndStrideOpInterface
   ]> {
@@ -519,7 +519,7 @@ def AIE_NpuDmaMemcpyNdOp: AIEX_Op<"ipu.dma_memcpy_nd", [
   let hasVerifier = 1;
 }
 
-def AIE_NpuDmaWaitOp: AIEX_Op<"ipu.dma_wait", []> {
+def AIE_NpuDmaWaitOp: AIEX_Op<"npu.dma_wait", []> {
   let summary = "Blocking operation to wait for a DMA to complete execution.";
   let description = [{
     The NpuDmaWaitOp blocks until the DMA referenced through `symbol` completes execution
@@ -530,13 +530,13 @@ def AIE_NpuDmaWaitOp: AIEX_Op<"ipu.dma_wait", []> {
       ...
       aie.objectfifo @out0(%tile_0_1, {%tile_0_0}, 4 : i32) : !aie.objectfifo<memref<32x32xi32>>
       ...
-      aiex.ipu.dma_memcpy_nd(0, 0, %arg2[1, 1, 0, 0][1, 1, 32, 32][1, 1, 64]) {id = 0 : i64, issue_token = true, metadata = @out0} : memref<32x64xi32>
+      aiex.npu.dma_memcpy_nd(0, 0, %arg2[1, 1, 0, 0][1, 1, 32, 32][1, 1, 64]) {id = 0 : i64, issue_token = true, metadata = @out0} : memref<32x64xi32>
       ...
-      aiex.ipu.dma_wait { symbol = @out0 }
+      aiex.npu.dma_wait { symbol = @out0 }
     ```
     Here, we have an objectfifo with symbol name `out0`, which is then referenced in the
-    `ipu.dma_memcpy_nd` operation as the target for the respective DMA operation. Afterwards,
-    an `ipu.dma_wait` operation references the same symbol to block until the respective DMA
+    `npu.dma_memcpy_nd` operation as the target for the respective DMA operation. Afterwards,
+    an `npu.dma_wait` operation references the same symbol to block until the respective DMA
     has executed all of its tasks.
   }];
   let arguments = (
@@ -549,7 +549,7 @@ def AIE_NpuDmaWaitOp: AIEX_Op<"ipu.dma_wait", []> {
 }
 
 // Write RTP
-def AIE_NpuWriteRTPOp: AIEX_Op<"ipu.rtp_write", []> {
+def AIE_NpuWriteRTPOp: AIEX_Op<"npu.rtp_write", []> {
   let summary = "rtp write operator";
   let arguments = (
     ins StrAttr:$buffer_sym_name,
@@ -567,7 +567,7 @@ def AIE_NpuWriteRTPOp: AIEX_Op<"ipu.rtp_write", []> {
 }
 
 // Push BD to Queue
-def AIE_NpuShimTilePushQueueOp: AIEX_Op<"ipu.shimtile_push_queue", []> {
+def AIE_NpuShimTilePushQueueOp: AIEX_Op<"npu.shimtile_push_queue", []> {
   let summary = "bd queue push operator";
   let arguments = (
     ins FlatSymbolRefAttr:$metadata,
@@ -586,7 +586,7 @@ def AIE_NpuShimTilePushQueueOp: AIEX_Op<"ipu.shimtile_push_queue", []> {
 }
 
 // WRITE32
-def AIE_NpuWrite32Op: AIEX_Op<"ipu.write32", []> {
+def AIE_NpuWrite32Op: AIEX_Op<"npu.write32", []> {
   let summary = "write32 operator";
   let arguments = (
     ins I32Attr:$column,
@@ -604,7 +604,7 @@ def AIE_NpuWrite32Op: AIEX_Op<"ipu.write32", []> {
 }
 
 // OP_SYNC
-def AIE_NpuSyncOp: AIEX_Op<"ipu.sync", []> {
+def AIE_NpuSyncOp: AIEX_Op<"npu.sync", []> {
   let summary = "sync operator";
   let arguments = (
     ins I32Attr:$column,
@@ -624,7 +624,7 @@ def AIE_NpuSyncOp: AIEX_Op<"ipu.sync", []> {
 }
 
 // WRITEBD_EXTEND_SHIMTILE
-def AIE_NpuWriteBdExShimTileOp: AIEX_Op<"ipu.writebd_shimtile", []> {
+def AIE_NpuWriteBdExShimTileOp: AIEX_Op<"npu.writebd_shimtile", []> {
   let summary = "dma operator";
   let arguments = (
     ins I32Attr:$column,

include/aie/Dialect/AIEX/Transforms/AIEXPasses.td

@@ -133,7 +133,7 @@ def AIELowerMemcpy : Pass<"aie-lower-memcpy", "AIE::DeviceOp"> {
   ];
 }
 
-def AIEDmaToNpu : Pass<"aie-dma-to-ipu", "AIE::DeviceOp"> {
+def AIEDmaToNpu : Pass<"aie-dma-to-npu", "AIE::DeviceOp"> {
   let summary = "";
   let description = [{
 

lib/CAPI/Translation.cpp

@@ -77,14 +77,14 @@ aieTranslateToCDODirect(MlirOperation moduleOp, MlirStringRef workDirPath,
 }
 
 MlirStringRef aieTranslateToNPU(MlirOperation moduleOp) {
-  std::string ipu;
-  llvm::raw_string_ostream os(ipu);
+  std::string npu;
+  llvm::raw_string_ostream os(npu);
   ModuleOp mod = llvm::cast<ModuleOp>(unwrap(moduleOp));
   if (failed(AIETranslateToNPU(mod, os)))
     return mlirStringRefCreate(nullptr, 0);
-  char *cStr = static_cast<char *>(malloc(ipu.size()));
-  ipu.copy(cStr, ipu.size());
-  return mlirStringRefCreate(cStr, ipu.size());
+  char *cStr = static_cast<char *>(malloc(npu.size()));
+  npu.copy(cStr, npu.size());
+  return mlirStringRefCreate(cStr, npu.size());
 }
 
 MlirStringRef aieTranslateToXAIEV2(MlirOperation moduleOp) {

lib/Dialect/AIE/IR/AIEDialect.cpp

@@ -983,7 +983,7 @@ const AIETargetModel &DeviceOp::getTargetModel() {
     return VE2302model;
   case AIEDevice::xcve2802:
     return VE2802model;
-  case AIEDevice::ipu:
+  case AIEDevice::npu:
     return NPUmodel;
   }
   return VC1902model;

lib/Targets/AIETargetCDODirect.cpp

@@ -265,7 +265,7 @@ LogicalResult configureBdInBlock(XAie_DevInst &devInst, XAie_DmaDesc &dmaTileBd,
     // write them out like this so they show up with names in debug prints
     size_t smid = 0;
     size_t burstLen = 16; // (10):BLEN=16 (256Byte) (corresponds to
-                          // 0x800000000 from targetipu)
+                          // 0x800000000 from target)
     size_t qOs = 0;
     size_t cache = 0;
     size_t secure = 0;
@@ -559,7 +559,7 @@ struct AIEControl {
       int32_t col = switchboxOp.colIndex();
       int32_t row = switchboxOp.rowIndex();
       XAie_LocType tileLoc = XAie_TileLoc(col, row);
-      assert(targetOp.getDevice() == AIEDevice::ipu &&
+      assert(targetOp.getDevice() == AIEDevice::npu &&
              "Only NPU currently supported");
       if (row == 0) {
         // FIXME hack for TCT routing
@@ -781,7 +781,7 @@ LogicalResult AIETranslateToCDODirect(ModuleOp m, llvm::StringRef workDirPath,
   DeviceOp targetOp = *devOps.begin();
   // things like XAIE_MEM_TILE_ROW_START and the missing
   // shim dma on tile (0,0) are hard-coded assumptions about NPU...
-  assert(targetOp.getDevice() == AIEDevice::ipu &&
+  assert(targetOp.getDevice() == AIEDevice::npu &&
          "Only NPU currently supported");
   int maxCol = 0, minCol = 0;
   for (auto tileOp : targetOp.getOps<TileOp>()) {

lib/Targets/AIETargets.cpp

@@ -321,7 +321,7 @@ void registerAIETranslations() {
       },
       registerDialects);
   TranslateFromMLIRRegistration registrationNPU(
-      "aie-ipu-instgen", "Generate instructions for NPU",
+      "aie-npu-instgen", "Generate instructions for NPU",
       [](ModuleOp module, raw_ostream &output) {
         return AIETranslateToNPU(module, output);
       },

python/AIEMLIRModule.cpp

@@ -107,11 +107,11 @@ PYBIND11_MODULE(_aie, m) {
       "enable_cores"_a = true);
 
   m.def(
-      "ipu_instgen",
+      "npu_instgen",
       [&stealCStr](MlirOperation op) {
-        py::str ipuInstructions = stealCStr(aieTranslateToNPU(op));
+        py::str npuInstructions = stealCStr(aieTranslateToNPU(op));
         auto individualInstructions =
-            ipuInstructions.attr("split")().cast<py::list>();
+            npuInstructions.attr("split")().cast<py::list>();
         for (size_t i = 0; i < individualInstructions.size(); ++i)
           individualInstructions[i] = individualInstructions[i].attr("strip")();
         return individualInstructions;

python/XRTModule.cpp

@@ -25,8 +25,8 @@
 namespace py = pybind11;
 using namespace py::literals;
 
-// group_id 0 is for ipu instructions
-// group_id 1 is for number of ipu instructions
+// group_id 0 is for npu instructions
+// group_id 1 is for number of npu instructions
 // host side buffers/args follow starting from position 2
 // see aiecc.main.emit_design_kernel_json
 constexpr size_t HOST_BUFFERS_START_IDX = 2;
@@ -45,13 +45,13 @@ class PyXCLBin {
   }
 
   void loadNPUInstructions(const std::vector<uint32_t> &insts) {
-    ipuInstructions =
+    npuInstructions =
         std::make_unique<xrt::bo>(*device, insts.size() * sizeof(uint32_t),
                                   XCL_BO_FLAGS_CACHEABLE, kernel->group_id(0));
-    uint32_t *bufInstr = ipuInstructions->map<uint32_t *>();
+    uint32_t *bufInstr = npuInstructions->map<uint32_t *>();
     for (size_t i = 0; i < insts.size(); ++i)
       bufInstr[i] = insts.at(i);
-    ipuInstructions->sync(XCL_BO_SYNC_BO_TO_DEVICE);
+    npuInstructions->sync(XCL_BO_SYNC_BO_TO_DEVICE);
   }
 
   template <typename ElementT>
@@ -107,17 +107,17 @@ class PyXCLBin {
 
   void run() {
     run_ = std::make_unique<xrt::run>(*kernel);
-    run_->set_arg(0, *ipuInstructions);
-    run_->set_arg(1, ipuInstructions->size());
+    run_->set_arg(0, *npuInstructions);
+    run_->set_arg(1, npuInstructions->size());
     for (size_t i = 0; i < buffers.size(); ++i)
       run_->set_arg(HOST_BUFFERS_START_IDX + i, *buffers[i]);
     run_->start();
   }
 
   void _runOnlyNpuInstructions() {
     run_ = std::make_unique<xrt::run>(*kernel);
-    run_->set_arg(0, *ipuInstructions);
-    run_->set_arg(1, ipuInstructions->size());
+    run_->set_arg(0, *npuInstructions);
+    run_->set_arg(1, npuInstructions->size());
     run_->start();
   }
 
@@ -133,7 +133,7 @@ class PyXCLBin {
   std::unique_ptr<xrt::device> device;
   std::unique_ptr<xrt::hw_context> context;
   std::unique_ptr<xrt::kernel> kernel;
-  std::unique_ptr<xrt::bo> ipuInstructions;
+  std::unique_ptr<xrt::bo> npuInstructions;
 
   std::vector<std::unique_ptr<xrt::bo>> buffers;
 
@@ -145,11 +145,11 @@ PYBIND11_MODULE(_xrt, m) {
   py::class_<PyXCLBin>(m, "XCLBin", py::module_local())
       .def(py::init<const std::string &, const std::string &, int>(),
            "xclbin_path"_a, "kernel_name"_a, "device_index"_a = 0)
-      .def("load_ipu_instructions", &PyXCLBin::loadNPUInstructions, "insts"_a)
+      .def("load_npu_instructions", &PyXCLBin::loadNPUInstructions, "insts"_a)
       .def("sync_buffers_to_device", &PyXCLBin::syncBuffersToDevice)
       .def("sync_buffers_from_device", &PyXCLBin::syncBuffersFromDevice)
       .def("run", &PyXCLBin::run)
-      .def("_run_only_ipu_instructions", &PyXCLBin::_runOnlyNpuInstructions)
+      .def("_run_only_npu_instructions", &PyXCLBin::_runOnlyNpuInstructions)
       .def("wait", &PyXCLBin::wait, "timeout"_a = py::none())
       .def(
           "mmap_buffers",

python/_mlir_libs/_aie.pyi

@@ -11,7 +11,7 @@ __all__ = [
     "generate_bcf",
     "generate_cdo",
     "generate_xaie",
-    "ipu_instgen",
+    "npu_instgen",
     "register_dialect",
     "translate_aie_vec_to_cpp",
     "translate_mlir_to_llvmir",
@@ -31,7 +31,7 @@ def generate_cdo(
     enable_cores: bool = True,
 ) -> None: ...
 def generate_xaie(module: Operation) -> str: ...
-def ipu_instgen(module: Operation) -> list: ...
+def npu_instgen(module: Operation) -> list: ...
 def register_dialect(registry: DialectRegistry) -> None: ...
 def translate_aie_vec_to_cpp(module: Operation, aieml: bool = False) -> str: ...
 def translate_mlir_to_llvmir(module: Operation) -> str: ...

python/_mlir_libs/_xrt.pyi

@@ -8,8 +8,8 @@ class XCLBin:
         self, xclbin_path: str, kernel_name: str, device_index: int = 0
     ) -> None: ...
     def _get_buffer_host_address(self, arg0: int) -> int: ...
-    def _run_only_ipu_instructions(self) -> None: ...
-    def load_ipu_instructions(self, insts: list[int]) -> None: ...
+    def _run_only_npu_instructions(self) -> None: ...
+    def load_npu_instructions(self, insts: list[int]) -> None: ...
     def mmap_buffers(
         self, shapes: list[list[int]], np_format: typing.Any
     ) -> list[memoryview]: ...

python/compiler/aiecc/cl_arguments.py

@@ -195,25 +195,25 @@ def parse_args(args=None):
         help="Show progress visualization",
     )
     parser.add_argument(
-        "--aie-generate-ipu",
-        dest="ipu",
+        "--aie-generate-npu",
+        dest="npu",
         default=False,
         action="store_const",
         const=True,
-        help="Generate ipu instruction stream",
+        help="Generate npu instruction stream",
     )
     parser.add_argument(
-        "--aie-only-generate-ipu",
-        dest="only_ipu",
+        "--aie-only-generate-npu",
+        dest="only_npu",
         default=False,
         action="store_const",
         const=True,
-        help="Generate ipu instruction stream only",
+        help="Generate npu instruction stream only",
     )
     parser.add_argument(
-        "--ipu-insts-name",
+        "--npu-insts-name",
         dest="insts_name",
-        default="ipu_insts.txt",
+        default="npu_insts.txt",
         help="Output instructions filename for NPU target",
     )
     parser.add_argument(

python/compiler/aiecc/main.py

@@ -89,7 +89,7 @@
 CREATE_PATH_FINDER_FLOWS = Pipeline().Nested(
     "aie.device", Pipeline().add_pass("aie-create-pathfinder-flows")
 )
-DMA_TO_NPU = Pipeline().Nested("aie.device", Pipeline().add_pass("aie-dma-to-ipu"))
+DMA_TO_NPU = Pipeline().Nested("aie.device", Pipeline().add_pass("aie-dma-to-npu"))
 
 
 async def read_file_async(file_path: str) -> str:
@@ -1014,13 +1014,13 @@ async def run_flow(self):
             aie_peano_target = aie_target.lower() + "-none-elf"
 
             # Optionally generate insts.txt for NPU instruction stream
-            if opts.ipu or opts.only_ipu:
-                generated_insts_mlir = self.prepend_tmp("generated_ipu_insts.mlir")
+            if opts.npu or opts.only_npu:
+                generated_insts_mlir = self.prepend_tmp("generated_npu_insts.mlir")
                 await self.do_call(
                     progress_bar.task,
                     [
                         "aie-opt",
-                        "--aie-dma-to-ipu",
+                        "--aie-dma-to-npu",
                         file_with_addresses,
                         "-o",
                         generated_insts_mlir,
@@ -1030,13 +1030,13 @@ async def run_flow(self):
                     progress_bar.task,
                     [
                         "aie-translate",
-                        "--aie-ipu-instgen",
+                        "--aie-npu-instgen",
                         generated_insts_mlir,
                         "-o",
                         opts.insts_name,
                     ],
                 )
-                if opts.only_ipu:
+                if opts.only_npu:
                     return
 
             chess_intrinsic_wrapper_ll_path = await self.prepare_for_chesshack(

python/dialects/aie.py

@@ -21,7 +21,7 @@
     generate_bcf,
     generate_cdo,
     generate_xaie,
-    ipu_instgen,
+    npu_instgen,
     register_dialect,
     translate_aie_vec_to_cpp,
     translate_mlir_to_llvmir,
@@ -617,7 +617,7 @@ def find_neighbors(tile, device=None, logical=True):
     if device is None:
         device = find_parent_of_type(lambda op: isinstance(op, DeviceOp))
 
-    assert int(device.device) == int(AIEDevice.ipu), "only ipu supported"
+    assert int(device.device) == int(AIEDevice.npu), "only npu supported"
 
     neighbors = {}
     col, row = map(int, (tile.col, tile.row))