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Switch to txn 1.0 format (#1676)
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@fifield
fifield authored Aug 16, 2024
1 parent ac9164a commit 59153bf
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Showing 3 changed files with 40 additions and 58 deletions.
67 changes: 32 additions & 35 deletions lib/Targets/AIETargetNPU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ void appendSync(std::vector<uint32_t> &instructions, NpuSyncOp op) {

void appendWrite32(std::vector<uint32_t> &instructions, NpuWrite32Op op) {

auto words = reserveAndGetTail(instructions, 6);
auto words = reserveAndGetTail(instructions, 3);

if (op.getBuffer()) {
op.emitOpError("Cannot translate symbolic address");
Expand All @@ -78,24 +78,21 @@ void appendWrite32(std::vector<uint32_t> &instructions, NpuWrite32Op op) {

// XAIE_IO_WRITE
words[0] = TXN_OPC_WRITE;
words[1] = 0;
words[2] = op.getAddress();
words[1] = op.getAddress();
auto col = op.getColumn();
auto row = op.getRow();
if (col && row) {
const AIETargetModel &tm = op->getParentOfType<DeviceOp>().getTargetModel();
words[2] = ((*col & 0xff) << tm.getColumnShift()) |
((*row & 0xff) << tm.getRowShift()) | (words[2] & 0xFFFFF);
words[1] = ((*col & 0xff) << tm.getColumnShift()) |
((*row & 0xff) << tm.getRowShift()) | (words[1] & 0xFFFFF);
}
words[3] = 0;
words[4] = op.getValue(); // Value
words[5] = words.size() * sizeof(uint32_t); // Operation Size
words[2] = op.getValue(); // Value
}

void appendMaskWrite32(std::vector<uint32_t> &instructions,
NpuMaskWrite32Op op) {

auto words = reserveAndGetTail(instructions, 7);
auto words = reserveAndGetTail(instructions, 4);

if (op.getBuffer()) {
op.emitOpError("Cannot translate symbolic address");
Expand All @@ -104,38 +101,33 @@ void appendMaskWrite32(std::vector<uint32_t> &instructions,

// XAIE_IO_MASKWRITE
words[0] = TXN_OPC_MASKWRITE;
words[1] = 0;
words[2] = op.getAddress();
words[1] = op.getAddress();
auto col = op.getColumn();
auto row = op.getRow();
if (col && row) {
const AIETargetModel &tm = op->getParentOfType<DeviceOp>().getTargetModel();
words[2] = ((*col & 0xff) << tm.getColumnShift()) |
((*row & 0xff) << tm.getRowShift()) | (words[2] & 0xFFFFF);
words[1] = ((*col & 0xff) << tm.getColumnShift()) |
((*row & 0xff) << tm.getRowShift()) | (words[1] & 0xFFFFF);
}
words[3] = 0;
words[4] = op.getValue(); // Value
words[5] = op.getMask();
words[6] = words.size() * sizeof(uint32_t); // Operation Size
words[2] = op.getValue(); // Value
words[3] = op.getMask();
}

void appendAddressPatch(std::vector<uint32_t> &instructions,
NpuAddressPatchOp op) {

auto words = reserveAndGetTail(instructions, 12);
auto words = reserveAndGetTail(instructions, 6);

// XAIE_IO_CUSTOM_OP_DDR_PATCH
words[0] = TXN_OPC_DDR_PATCH;
words[1] = words.size() * sizeof(uint32_t); // Operation Size

words[6] = op.getAddr();
words[7] = 0;
words[2] = op.getAddr();

words[8] = op.getArgIdx();
words[9] = 0;
words[3] = op.getArgIdx();

words[10] = op.getArgPlus();
words[11] = 0;
words[4] = op.getArgPlus();
words[5] = 0;
}

void appendBlockWrite(std::vector<uint32_t> &instructions, NpuBlockWriteOp op) {
Expand Down Expand Up @@ -172,22 +164,21 @@ void appendBlockWrite(std::vector<uint32_t> &instructions, NpuBlockWriteOp op) {
return;
}

auto words = reserveAndGetTail(instructions, data.size() + 4);
auto words = reserveAndGetTail(instructions, data.size() + 3);

// XAIE_IO_BLOCKWRITE
words[0] = TXN_OPC_BLOCKWRITE;
words[1] = 0;
words[2] = op.getAddress();
words[1] = op.getAddress();
auto col = op.getColumn();
auto row = op.getRow();
if (col && row) {
const AIETargetModel &tm = op->getParentOfType<DeviceOp>().getTargetModel();
words[2] = ((*col & 0xff) << tm.getColumnShift()) |
((*row & 0xff) << tm.getRowShift()) | (words[2] & 0xFFFFF);
words[1] = ((*col & 0xff) << tm.getColumnShift()) |
((*row & 0xff) << tm.getRowShift()) | (words[1] & 0xFFFFF);
}
words[3] = words.size() * sizeof(uint32_t); // Operation Size
words[2] = words.size() * sizeof(uint32_t); // Operation Size

unsigned i = 4;
unsigned i = 3;
for (auto d : data)
words[i++] = d.getZExtValue();
}
Expand All @@ -201,12 +192,18 @@ std::vector<uint32_t> xilinx::AIE::AIETranslateToNPU(ModuleOp module) {
auto words = reserveAndGetTail(instructions, 4);

// setup txn header
words[0] = 0x06030100;
words[1] = 0x00000105;
uint8_t major = 1;
uint8_t minor = 0;
uint8_t devGen = 3;
uint8_t numRows = 6;
uint8_t numCols = 5;
uint8_t numMemTileRows = 1;
uint32_t count = 0;
words[0] = (numRows << 24) | (devGen << 16) | (minor << 8) | major;
words[1] = (numMemTileRows << 8) | numCols;

DeviceOp deviceOp = *module.getOps<DeviceOp>().begin();
auto sequenceOps = deviceOp.getOps<AIEX::RuntimeSequenceOp>();
int count = 0;
for (auto f : sequenceOps) {
Block &entry = f.getBody().front();
for (auto &o : entry) {
Expand Down Expand Up @@ -236,7 +233,7 @@ std::vector<uint32_t> xilinx::AIE::AIETranslateToNPU(ModuleOp module) {

// write size fields of the txn header
instructions[2] = count;
instructions[3] = instructions.size() * sizeof(uint32_t);
instructions[3] = instructions.size() * sizeof(uint32_t); // size of the txn
return instructions;
}

Expand Down
10 changes: 3 additions & 7 deletions test/Targets/NPU/npu_blockwrite_instgen.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -14,21 +14,19 @@ module {
aiex.runtime_sequence(%arg0: memref<16xf32>, %arg1: memref<16xf32>) {

// TXN header
// CHECK: 06030100
// CHECK: 06030001
// CHECK: 00000105
// CHECK: 00000003
// CHECK: 00000068
// CHECK: 00000058

%c16_i64 = arith.constant 16 : i64
%c1_i64 = arith.constant 1 : i64
%c0_i64 = arith.constant 0 : i64
%c64_i64 = arith.constant 64 : i64
%c0_i32 = arith.constant 0 : i32
%c1_i32 = arith.constant 1 : i32
// CHECK: 00000001
// CHECK: 00000000
// CHECK: 061A00C0
// CHECK: 00000030
// CHECK: 0000002C
// CHECK: 00000001
// CHECK: 00580002
// CHECK: 000C0005
Expand Down Expand Up @@ -64,9 +62,7 @@ module {
use_next_bd = 1 : i32,
valid_bd = 1 : i32}
// CHECK: 00000000
// CHECK: 00000000
// CHECK: 06400DEF
// CHECK: 00000000
// CHECK: 00000042
aiex.npu.write32 { column = 3 : i32, row = 4 : i32, address = 0xabc00def : ui32, value = 0x42 : ui32 }

Expand Down
21 changes: 5 additions & 16 deletions test/Targets/NPU/npu_instgen.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -14,32 +14,25 @@ module {
memref.global "private" constant @write_data : memref<8xi32> = dense<[100, 101, 102, 103, 104 ,105, 106, 107]>
aiex.runtime_sequence(%arg0: memref<16xf32>, %arg1: memref<16xf32>) {

// TXN header
// CHECK: 06030100
// TXN header 1.0
// CHECK: 06030001
// CHECK: 00000105
// CHECK: 00000006
// CHECK: 000000CC
// CHECK: 000000A0

// CHECK: 00000000
// CHECK: 00000000
// CHECK: 06400DEF
// CHECK: 00000000
// CHECK: 00000042
// CHECK: 00000018
aiex.npu.write32 { column = 3 : i32, row = 4 : i32, address = 0xabc00def : ui32, value = 0x42 : ui32 }

// CHECK: 00000000
// CHECK: 00000000
// CHECK: ABC00DEF
// CHECK: 00000000
// CHECK: 00000314
// CHECK: 00000018
aiex.npu.write32 { address = 0xabc00def : ui32, value = 0x314 : ui32 }

// CHECK: 00000001
// CHECK: 00000000
// CHECK: 12345679
// CHECK: 00000030
// CHECK: 0000002C
// CHECK: 00000064
// CHECK: 00000065
// CHECK: 00000066
Expand All @@ -52,9 +45,8 @@ module {
aiex.npu.blockwrite (%0) {address = 0x12345679 : ui32} : memref<8xi32>

// CHECK: 00000001
// CHECK: 00000000
// CHECK: 02100064
// CHECK: 00000030
// CHECK: 0000002C
// CHECK: 00000064
// CHECK: 00000065
// CHECK: 00000066
Expand All @@ -66,12 +58,9 @@ module {
aiex.npu.blockwrite (%0) { column = 1 : i32, row = 1 : i32, address = 100 : ui32} : memref<8xi32>

// CHECK: 00000003
// CHECK: 00000000
// CHECK: 0430567A
// CHECK: 00000000
// CHECK: 00001001
// CHECK: F00FF00F
// CHECK: 0000001C
aiex.npu.maskwrite32 { column = 2 : i32, row = 3 : i32, address = 0x0000567A : ui32, value = 0x1001 : ui32, mask = 0xf00ff00f : ui32 }

// CHECK: 00000080
Expand Down

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