replace "ipu" with "npu" (#1305)

docs/buildHostLin.md

@@ -293,7 +293,7 @@ source ${MLIR_AIE_BUILD_DIR}/utils/env_setup.sh ${MLIR_AIE_BUILD_DIR}/install ${
 
 ## Build a Design
 
-For your design of interest, for instance [add_one_objFifo](../reference_designs/ipu-xrt/add_one_objFifo/), 2 steps are needed: (i) build the AIE desgin and then (ii) build the host code.
+For your design of interest, for instance [vector_add](../programming_examples/basic/vector_add/), 2 steps are needed: (i) build the AIE desgin and then (ii) build the host code.
 
 ### Build Device AIE Part
 

docs/buildHostWin.md

@@ -58,7 +58,7 @@ All steps in WSL Ubuntu terminal.
 
 1. After installing the updated RyzenAI driver (see next subsection), use the gendef tool (from the mingw-w64-tools package) to create a .def file with the symbols:
     ```
-    mkdir /mnt/c/Technical/xrtIPUfromDLL; cd /mnt/c/Technical/xrtIPUfromDLL
+    mkdir /mnt/c/Technical/xrtNPUfromDLL; cd /mnt/c/Technical/xrtNPUfromDLL
     cp /mnt/c/Windows/System32/AMD/xrt_coreutil.dll .
     gendef xrt_coreutil.dll
     ```
@@ -67,7 +67,7 @@ All steps in WSL Ubuntu terminal.
 
 All steps in Win11 (powershell where needed).
 
-1. Upgrade the IPU driver IPU driver to version 10.106.8.62 [download here](https://account.amd.com/en/forms/downloads/ryzen-ai-software-platform-xef.html?filename=ipu_stack_rel_silicon_2308.zip), following the [instructions](href="https://ryzenai.docs.amd.com/en/latest/inst.html) on setting up the driver.
+1. Upgrade the NPU driver to version 10.106.8.62 [download here](https://account.amd.com/en/forms/downloads/ryzen-ai-software-platform-xef.html?filename=ipu_stack_rel_silicon_2308.zip), following the [instructions](href="https://ryzenai.docs.amd.com/en/latest/inst.html) on setting up the driver.
 1. Install [Microsoft Visual Studio 17 2022 Community Edition](https://visualstudio.microsoft.com/vs/community/) with package for C++ development.
 
 1. Install CMake on windows ([https://cmake.org/download/](https://cmake.org/download/))
@@ -79,7 +79,7 @@ All steps in Win11 (powershell where needed).
 1. Clone [https://github.com/Xilinx/XRT](https://github.com/Xilinx/XRT) for instance under `C:\Technical` and `git checkout 2023.2`
 1. Create a .lib file from the .dll shipping with the driver
     - In wsl, generate a .def file (see above)
-    - Start a x86 Native Tools Command Prompt (installed as part of VS17), go to the folder `C:\Technical\xrtIPUfromDLL` and run command: 
+    - Start a x86 Native Tools Command Prompt (installed as part of VS17), go to the folder `C:\Technical\xrtNPUfromDLL` and run command: 
       ```
       lib /def:xrt_coreutil.def /machine:x64 /out:xrt_coreutil.lib
       ```
@@ -113,7 +113,7 @@ source <yourPathToBuildMLIR-AIE>/utils/env_setup.sh <yourPathToBuildMLIR-AIE>/in
 
 ## Build a Design
 
-For your design of interest, for instance [add_one_objFifo](../reference_designs/ipu-xrt/add_one_objFifo/), 2 steps are needed: (i) build the AIE desgin in WSL and then (ii) build the host code in powershell.
+For your design of interest, for instance [vector_add](../programming_examples/basic/vector_add/), 2 steps are needed: (i) build the AIE desgin in WSL and then (ii) build the host code in powershell.
 
 ### Build device AIE part: WSL Ubuntu terminal
 1. Prepare your enviroment with the mlir-aie tools (built during Prerequisites part of this guide). See [Set up your environment](#set-up-your-environment) above.

include/aie-c/Translation.h

@@ -18,7 +18,7 @@ extern "C" {
 MLIR_CAPI_EXPORTED MlirStringRef aieTranslateAIEVecToCpp(MlirOperation op,
                                                          bool aieml);
 MLIR_CAPI_EXPORTED MlirStringRef aieTranslateModuleToLLVMIR(MlirOperation op);
-MLIR_CAPI_EXPORTED MlirStringRef aieTranslateToIPU(MlirOperation op);
+MLIR_CAPI_EXPORTED MlirStringRef aieTranslateToNPU(MlirOperation op);
 MLIR_CAPI_EXPORTED MlirStringRef aieTranslateToXAIEV2(MlirOperation op);
 MLIR_CAPI_EXPORTED MlirStringRef aieTranslateToHSA(MlirOperation op);
 MLIR_CAPI_EXPORTED MlirStringRef aieTranslateToBCF(MlirOperation op, int col,

include/aie/Dialect/AIE/IR/AIEAttrs.td

@@ -100,7 +100,7 @@ def AIEDevice: I32EnumAttr<"AIEDevice", "AIE Device",
     I32EnumAttrCase<"xcvc1902", 1>,
     I32EnumAttrCase<"xcve2302", 2>,
     I32EnumAttrCase<"xcve2802", 3>,
-    I32EnumAttrCase<"ipu", 4>
+    I32EnumAttrCase<"npu", 4>
   ]> {
 
   let cppNamespace = "xilinx::AIE";

include/aie/Dialect/AIE/IR/AIETargetModel.h

@@ -450,11 +450,11 @@ class VE2802TargetModel : public AIE2TargetModel {
   }
 };
 
-class IPUTargetModel : public AIE2TargetModel {
+class NPUTargetModel : public AIE2TargetModel {
   llvm::SmallDenseSet<unsigned, 16> nocColumns = {0, 1, 2, 3};
 
 public:
-  IPUTargetModel() = default;
+  NPUTargetModel() = default;
 
   int columns() const override { return 5; }
 

include/aie/Dialect/AIEX/IR/AIEX.td

@@ -463,7 +463,7 @@ def AIE_SelectOp: AIEX_Op<"select", []>, Results<(outs Index)> {
   ];
 }
 
-def AIE_IpuDmaMemcpyNdOp: AIEX_Op<"ipu.dma_memcpy_nd", [
+def AIE_NpuDmaMemcpyNdOp: AIEX_Op<"npu.dma_memcpy_nd", [
     AttrSizedOperandSegments,
     MyOffsetSizeAndStrideOpInterface
   ]> {
@@ -519,24 +519,24 @@ def AIE_IpuDmaMemcpyNdOp: AIEX_Op<"ipu.dma_memcpy_nd", [
   let hasVerifier = 1;
 }
 
-def AIE_IpuDmaWaitOp: AIEX_Op<"ipu.dma_wait", []> {
+def AIE_NpuDmaWaitOp: AIEX_Op<"npu.dma_wait", []> {
   let summary = "Blocking operation to wait for a DMA to complete execution.";
   let description = [{
-    The IpuDmaWaitOp blocks until the DMA referenced through `symbol` completes execution
+    The NpuDmaWaitOp blocks until the DMA referenced through `symbol` completes execution
     and issues a task-complete-token.
 
     Example:
     ```mlir
       ...
       aie.objectfifo @out0(%tile_0_1, {%tile_0_0}, 4 : i32) : !aie.objectfifo<memref<32x32xi32>>
       ...
-      aiex.ipu.dma_memcpy_nd(0, 0, %arg2[1, 1, 0, 0][1, 1, 32, 32][1, 1, 64]) {id = 0 : i64, issue_token = true, metadata = @out0} : memref<32x64xi32>
+      aiex.npu.dma_memcpy_nd(0, 0, %arg2[1, 1, 0, 0][1, 1, 32, 32][1, 1, 64]) {id = 0 : i64, issue_token = true, metadata = @out0} : memref<32x64xi32>
       ...
-      aiex.ipu.dma_wait { symbol = @out0 }
+      aiex.npu.dma_wait { symbol = @out0 }
     ```
     Here, we have an objectfifo with symbol name `out0`, which is then referenced in the
-    `ipu.dma_memcpy_nd` operation as the target for the respective DMA operation. Afterwards,
-    an `ipu.dma_wait` operation references the same symbol to block until the respective DMA
+    `npu.dma_memcpy_nd` operation as the target for the respective DMA operation. Afterwards,
+    an `npu.dma_wait` operation references the same symbol to block until the respective DMA
     has executed all of its tasks.
   }];
   let arguments = (
@@ -549,7 +549,7 @@ def AIE_IpuDmaWaitOp: AIEX_Op<"ipu.dma_wait", []> {
 }
 
 // Write RTP
-def AIE_IpuWriteRTPOp: AIEX_Op<"ipu.rtp_write", []> {
+def AIE_NpuWriteRTPOp: AIEX_Op<"npu.rtp_write", []> {
   let summary = "rtp write operator";
   let arguments = (
     ins StrAttr:$buffer_sym_name,
@@ -567,7 +567,7 @@ def AIE_IpuWriteRTPOp: AIEX_Op<"ipu.rtp_write", []> {
 }
 
 // Push BD to Queue
-def AIE_IpuShimTilePushQueueOp: AIEX_Op<"ipu.shimtile_push_queue", []> {
+def AIE_NpuShimTilePushQueueOp: AIEX_Op<"npu.shimtile_push_queue", []> {
   let summary = "bd queue push operator";
   let arguments = (
     ins FlatSymbolRefAttr:$metadata,
@@ -586,7 +586,7 @@ def AIE_IpuShimTilePushQueueOp: AIEX_Op<"ipu.shimtile_push_queue", []> {
 }
 
 // WRITE32
-def AIE_IpuWrite32Op: AIEX_Op<"ipu.write32", []> {
+def AIE_NpuWrite32Op: AIEX_Op<"npu.write32", []> {
   let summary = "write32 operator";
   let arguments = (
     ins I32Attr:$column,
@@ -604,7 +604,7 @@ def AIE_IpuWrite32Op: AIEX_Op<"ipu.write32", []> {
 }
 
 // OP_SYNC
-def AIE_IpuSyncOp: AIEX_Op<"ipu.sync", []> {
+def AIE_NpuSyncOp: AIEX_Op<"npu.sync", []> {
   let summary = "sync operator";
   let arguments = (
     ins I32Attr:$column,
@@ -624,7 +624,7 @@ def AIE_IpuSyncOp: AIEX_Op<"ipu.sync", []> {
 }
 
 // WRITEBD_EXTEND_SHIMTILE
-def AIE_IpuWriteBdExShimTileOp: AIEX_Op<"ipu.writebd_shimtile", []> {
+def AIE_NpuWriteBdExShimTileOp: AIEX_Op<"npu.writebd_shimtile", []> {
   let summary = "dma operator";
   let arguments = (
     ins I32Attr:$column,

include/aie/Dialect/AIEX/Transforms/AIEXPasses.h

@@ -28,7 +28,7 @@ std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
 createAIELowerMulticastPass();
 std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>>
 createAIEBroadcastPacketPass();
-std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>> createAIEDmaToIpuPass();
+std::unique_ptr<mlir::OperationPass<AIE::DeviceOp>> createAIEDmaToNpuPass();
 std::unique_ptr<mlir::OperationPass<mlir::ModuleOp>> createAIEXToStandardPass();
 
 /// Generate the code for registering passes.

include/aie/Dialect/AIEX/Transforms/AIEXPasses.td

@@ -17,7 +17,7 @@ def AIEXToStandard : Pass<"aiex-standard-lowering", "mlir::ModuleOp"> {
   let summary = "Lower AIEX operations";
   let description = [{
 
-    AIEX Ipu Ops are removed.
+    AIEX Npu Ops are removed.
 
   }];
 
@@ -133,13 +133,13 @@ def AIELowerMemcpy : Pass<"aie-lower-memcpy", "AIE::DeviceOp"> {
   ];
 }
 
-def AIEDmaToIpu : Pass<"aie-dma-to-ipu", "AIE::DeviceOp"> {
+def AIEDmaToNpu : Pass<"aie-dma-to-npu", "AIE::DeviceOp"> {
   let summary = "";
   let description = [{
 
   }];
 
-  let constructor = "xilinx::AIEX::createAIEDmaToIpuPass()";
+  let constructor = "xilinx::AIEX::createAIEDmaToNpuPass()";
   let dependentDialects = [
     "mlir::func::FuncDialect",
     "xilinx::AIE::AIEDialect",

include/aie/Targets/AIETargets.h

@@ -31,9 +31,9 @@ mlir::LogicalResult AIETranslateShimSolution(mlir::ModuleOp module,
                                              llvm::raw_ostream &);
 mlir::LogicalResult AIETranslateGraphXPE(mlir::ModuleOp module,
                                          llvm::raw_ostream &);
-mlir::LogicalResult AIETranslateToIPU(mlir::ModuleOp module,
+mlir::LogicalResult AIETranslateToNPU(mlir::ModuleOp module,
                                       llvm::raw_ostream &output);
-std::vector<uint32_t> AIETranslateToIPU(mlir::ModuleOp);
+std::vector<uint32_t> AIETranslateToNPU(mlir::ModuleOp);
 mlir::LogicalResult AIETranslateToLdScript(mlir::ModuleOp module,
                                            llvm::raw_ostream &output,
                                            int tileCol, int tileRow);

lib/CAPI/Translation.cpp

@@ -76,15 +76,15 @@ aieTranslateToCDODirect(MlirOperation moduleOp, MlirStringRef workDirPath,
   return wrap(status);
 }
 
-MlirStringRef aieTranslateToIPU(MlirOperation moduleOp) {
-  std::string ipu;
-  llvm::raw_string_ostream os(ipu);
+MlirStringRef aieTranslateToNPU(MlirOperation moduleOp) {
+  std::string npu;
+  llvm::raw_string_ostream os(npu);
   ModuleOp mod = llvm::cast<ModuleOp>(unwrap(moduleOp));
-  if (failed(AIETranslateToIPU(mod, os)))
+  if (failed(AIETranslateToNPU(mod, os)))
     return mlirStringRefCreate(nullptr, 0);
-  char *cStr = static_cast<char *>(malloc(ipu.size()));
-  ipu.copy(cStr, ipu.size());
-  return mlirStringRefCreate(cStr, ipu.size());
+  char *cStr = static_cast<char *>(malloc(npu.size()));
+  npu.copy(cStr, npu.size());
+  return mlirStringRefCreate(cStr, npu.size());
 }
 
 MlirStringRef aieTranslateToXAIEV2(MlirOperation moduleOp) {

lib/Dialect/AIE/IR/AIEDialect.cpp

@@ -104,7 +104,7 @@ LogicalResult myVerifyOffsetSizeAndStrideOp(OffsetSizeAndStrideOpInterface op) {
 static VC1902TargetModel VC1902model;
 static VE2302TargetModel VE2302model;
 static VE2802TargetModel VE2802model;
-static IPUTargetModel IPUmodel;
+static NPUTargetModel NPUmodel;
 
 const AIETargetModel &getTargetModel(Operation *op) {
   if (auto t = dyn_cast<AIETarget>(op))
@@ -983,8 +983,8 @@ const AIETargetModel &DeviceOp::getTargetModel() {
     return VE2302model;
   case AIEDevice::xcve2802:
     return VE2802model;
-  case AIEDevice::ipu:
-    return IPUmodel;
+  case AIEDevice::npu:
+    return NPUmodel;
   }
   return VC1902model;
 }

lib/Dialect/AIEX/IR/AIEXDialect.cpp

@@ -64,7 +64,7 @@ LogicalResult AIEX::BroadcastPacketOp::verify() {
   return success();
 }
 
-LogicalResult AIEX::IpuDmaMemcpyNdOp::verify() {
+LogicalResult AIEX::NpuDmaMemcpyNdOp::verify() {
   MemRefType buffer = getMemref().getType();
   if (buffer.getElementTypeBitWidth() != 32)
     return emitOpError("must be used with memref type with element width 32.");
@@ -105,7 +105,7 @@ LogicalResult AIEX::IpuDmaMemcpyNdOp::verify() {
   return success();
 }
 
-LogicalResult AIEX::IpuDmaWaitOp::verify() {
+LogicalResult AIEX::NpuDmaWaitOp::verify() {
   AIE::DeviceOp dev = (*this)->getParentOfType<AIE::DeviceOp>();
   // Some passes (e.g. aie-standard-lowering) use aiex ops outside a DeviceOp,
   // so we can't expect the device to always exist.
@@ -114,7 +114,7 @@ LogicalResult AIEX::IpuDmaWaitOp::verify() {
   return success();
 }
 
-LogicalResult AIEX::IpuShimTilePushQueueOp::verify() {
+LogicalResult AIEX::NpuShimTilePushQueueOp::verify() {
   const auto &targetModel = AIE::getTargetModel(*this);
   auto numBds = targetModel.getNumBDs(0, 0); // assume shim
   if (getBdId() > numBds)
@@ -124,7 +124,7 @@ LogicalResult AIEX::IpuShimTilePushQueueOp::verify() {
   return success();
 }
 
-LogicalResult AIEX::IpuWriteBdExShimTileOp::verify() {
+LogicalResult AIEX::NpuWriteBdExShimTileOp::verify() {
   const auto &targetModel = AIE::getTargetModel(*this);
   auto numBds = targetModel.getNumBDs(0, 0); // assume shim
   if (getBdId() > numBds)