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[aievec] Add lowering for vector.extract_strided_slice
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This is part of the canonical lowering of unaligned transfer read ops.

For now we only support extracting a contiguous vector of half the size
of the source vector.
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jsetoain committed May 17, 2023
1 parent da372f2 commit 9e5589b
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Showing 9 changed files with 552 additions and 133 deletions.
336 changes: 233 additions & 103 deletions lib/Dialect/AIEVec/Transforms/ConvertVectorToAIEVec.cpp

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43 changes: 30 additions & 13 deletions test/Conversion/VectorToAIEVec/test-upd.mlir
Original file line number Diff line number Diff line change
@@ -1,49 +1,66 @@
// RUN: aie-opt %s --convert-vector-to-aievec | FileCheck %s
// RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" | FileCheck %s --check-prefix=CHECK-V2
// RUN: aie-opt %s --convert-vector-to-aievec -split-input-file | FileCheck %s
// RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -split-input-file | FileCheck %s --check-prefix=CHECK-V2

// CHECK-V2-LABEL: func @veccopy_i8
func.func @veccopy_i8(%arg0: memref<256xi8>, %arg1: memref<256xi8>) {
%c0_i8 = arith.constant 0 : i8
affine.for %arg2 = 0 to 256 step 16 {
// CHECK: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi8>, vector<16xi8>
// CHECK-V2: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi8>, vector<16xi8>
%0 = vector.transfer_read %arg0[%arg2], %c0_i8 : memref<256xi8>, vector<16xi8>
// CHECK: vector.transfer_write %[[LD]], {{.*}}
// CHECK-V2: vector.transfer_write %[[LD]], {{.*}}
vector.transfer_write %0, %arg1[%arg2] : vector<16xi8>, memref<256xi8>
}
return
}

// -----

// CHECK-LABEL: func @veccopy_i16
// CHECK-V2-LABEL: func @veccopy_i16
func.func @veccopy_i16(%arg0: memref<256xi16>, %arg1: memref<256xi16>) {
%c0_i16 = arith.constant 0 : i16
affine.for %arg2 = 0 to 256 step 16 {
// CHECK: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi16>, vector<16xi16>
// CHECK-V2: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi16>, vector<16xi16>
%0 = vector.transfer_read %arg0[%arg2], %c0_i16 : memref<256xi16>, vector<16xi16>
// CHECK: vector.transfer_write %[[LD]], {{.*}}
// CHECK-V2: vector.transfer_write %[[LD]], {{.*}}
vector.transfer_write %0, %arg1[%arg2] : vector<16xi16>, memref<256xi16>
}
return
}

// -----

// CHECK-LABEL: func @veccopy_i32
// CHECK-V2-LABEL: func @veccopy_i32
func.func @veccopy_i32(%arg0: memref<256xi32>, %arg1: memref<256xi32>) {
%c0_i32 = arith.constant 0 : i32
affine.for %arg2 = 0 to 256 step 16 {
// CHECK: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi32>, vector<16xi32>
%0 = vector.transfer_read %arg0[%arg2], %c0_i32 : memref<256xi32>, vector<16xi32>
affine.for %arg2 = 0 to 256 step 8 {
// CHECK: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi32>, vector<8xi32>
// CHECK-V2: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi32>, vector<8xi32>
%0 = vector.transfer_read %arg0[%arg2], %c0_i32 : memref<256xi32>, vector<8xi32>
// CHECK: vector.transfer_write %[[LD]], {{.*}}
vector.transfer_write %0, %arg1[%arg2] : vector<16xi32>, memref<256xi32>
// CHECK-V2: vector.transfer_write %[[LD]], {{.*}}
vector.transfer_write %0, %arg1[%arg2] : vector<8xi32>, memref<256xi32>
}
return
}

// -----

// CHECK-LABEL: func @veccopy_long_i32
// CHECK-V2-LABEL: func @veccopy_long_i32
func.func @veccopy_long_i32(%arg0: memref<256xi32>, %arg1: memref<256xi32>) {
%c0_i32 = arith.constant 0 : i32
affine.for %arg2 = 0 to 256 step 32 {
// CHECK: %[[LD0:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi32>, vector<32xi32>
// CHECK-NEXT: %[[LD1:.*]] = aievec.upd {{.*}}, %[[LD0]] {index = 1 : i8, offset = 512 : si32} : memref<256xi32>, vector<32xi32>
affine.for %arg2 = 0 to 256 step 16 {
// CHECK: %[[LD0:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi32>, vector<16xi32>
// CHECK-NEXT: %[[LD1:.*]] = aievec.upd {{.*}}, %[[LD0]] {index = 1 : i8, offset = 256 : si32} : memref<256xi32>, vector<16xi32>
// CHECK-V2: %[[LD:.*]] = aievec.upd {{.*}} {index = 0 : i8, offset = 0 : si32} : memref<256xi32>, vector<16xi32>
%0 = vector.transfer_read %arg0[%arg2], %c0_i32 : memref<256xi32>, vector<32xi32>
%0 = vector.transfer_read %arg0[%arg2], %c0_i32 : memref<256xi32>, vector<16xi32>
// CHECK: vector.transfer_write %[[LD1]], {{.*}}
// CHECK-V2: vector.transfer_write %[[LD]], {{.*}}
vector.transfer_write %0, %arg1[%arg2] : vector<32xi32>, memref<256xi32>
vector.transfer_write %0, %arg1[%arg2] : vector<16xi32>, memref<256xi32>
}
return
}
82 changes: 65 additions & 17 deletions test/Conversion/VectorToAIEVec/unaligned-load.mlir
Original file line number Diff line number Diff line change
@@ -1,20 +1,68 @@
// RUN: aie-opt %s --convert-vector-to-aievec | FileCheck %s
func.func @unaligned_read(%a: memref<48xi8>) -> (vector<32xi8>, vector<32xi8>) {
%c0_i8 = arith.constant 0 : i8
%c16 = arith.constant 16 : index
%c34 = arith.constant 34 : index
%0 = vector.transfer_read %a[%c16], %c0_i8 : memref<48xi8>, vector<32xi8>
%1 = vector.transfer_read %a[%c34], %c0_i8 : memref<48xi8>, vector<32xi8>
return %0, %1 : vector<32xi8>, vector<32xi8>
// RUN: aie-opt %s --convert-vector-to-aievec -split-input-file | FileCheck %s
//func.func @unaligned_read(%a: memref<48xi8>) -> (vector<32xi8>, vector<32xi8>) {
// %c0_i8 = arith.constant 0 : i8
// %c16 = arith.constant 16 : index
// %c34 = arith.constant 34 : index
// %0 = vector.transfer_read %a[%c16], %c0_i8 : memref<48xi8>, vector<32xi8>
// %1 = vector.transfer_read %a[%c34], %c0_i8 : memref<48xi8>, vector<32xi8>
// return %0, %1 : vector<32xi8>, vector<32xi8>
//}

// C_HECK-LABEL: func @unaligned_read
// C_HECK : %[[C64:.*]] = arith.constant 64 : index
// C_HECK : %[[C32:.*]] = arith.constant 32 : index
// C_HECK : %[[C0:.*]] = arith.constant 0 : index
// C_HECK : %[[T0:.*]] = aievec.upd {{.*}}[%[[C0:.*]]] {index = 0 : i8, offset = 0 : si32} : memref<48xi8>, vector<32xi8>
// C_HECK : %[[T1:.*]] = aievec.upd {{.*}}[%[[C32:.*]]] {index = 0 : i8, offset = 0 : si32} : memref<48xi8>, vector<32xi8>
// C_HECK : %[[T2:.*]] = aievec.shift %[[T0:.*]], %[[T1:.*]] {shift = 16 : i32} : vector<32xi8>, vector<32xi8>
// C_HECK : %[[T3:.*]] = aievec.upd {{.*}}[%[[C64:.*]]] {index = 0 : i8, offset = 0 : si32} : memref<48xi8>, vector<32xi8>
// C_HECK : %[[T4:.*]] = aievec.shift %[[T1:.*]], %[[T3:.*]] {shift = 2 : i32} : vector<32xi8>, vector<32xi8>
// C_HECK : return %[[T2:.*]], %[[T4:.*]] : vector<32xi8>, vector<32xi8>

// -----

// CHECK-LABEL: func @unaligned_read
// CHECK: %[[C0:.*]] = arith.constant 0 : index
// CHECK: %[[V0B:.*]] = aievec.upd %{{.*}}[%[[C0]]] {index = 0 : i8, offset = 0 : si32} : memref<64xi32>, vector<16xi32>
// CHECK: %[[V0T:.*]] = aievec.upd %{{.*}}[%[[C0]]], %[[V0B]] {index = 1 : i8, offset = 256 : si32} : memref<64xi32>, vector<16xi32>
// CHECK: %[[V0ROT:.*]] = aievec.select %[[V0T]] {select = "0", xoffsets = "0x76543210", xsquare = "0x3210", xstart = "3",
// CHECK-SAME: yoffsets = "0", ysquare = "0", ystart = "0"}
// CHECK-SAME: : vector<16xi32>, vector<16xi32>
// CHECK: %[[V0:.*]] = aievec.ext %[[V0ROT]] {index = 0 : i8} : vector<16xi32>, vector<8xi32>
// CHECK: %[[V1ROT:.*]] = aievec.select %[[V0T]] {select = "0", xoffsets = "0x76543210", xsquare = "0x3210", xstart = "6",
// CHECK-SAME: yoffsets = "0", ysquare = "0", ystart = "0"}
// CHECK-SAME: : vector<16xi32>, vector<16xi32>
// CHECK: %[[V1:.*]] = aievec.ext %[[V1ROT]] {index = 0 : i8} : vector<16xi32>, vector<8xi32>
// CHECK: return %[[V0]], %[[V1]] : vector<8xi32>, vector<8xi32>
func.func @unaligned_read(%m: memref<64xi32>) -> (vector<8xi32>, vector<8xi32>) {
%c0_i32 = arith.constant 0 : i32
%c3 = arith.constant 3 : index
%c6 = arith.constant 6 : index
%0 = vector.transfer_read %m[%c3], %c0_i32 : memref<64xi32>, vector<8xi32>
%1 = vector.transfer_read %m[%c6], %c0_i32 : memref<64xi32>, vector<8xi32>
return %0, %1 : vector<8xi32>, vector<8xi32>
}

// -----

// CHECK-LABEL: func @unaligned_read
// CHECK : %[[C64:.*]] = arith.constant 64 : index
// CHECK : %[[C32:.*]] = arith.constant 32 : index
// CHECK : %[[C0:.*]] = arith.constant 0 : index
// CHECK : %[[T0:.*]] = aievec.upd {{.*}}[%[[C0:.*]]] {index = 0 : i8, offset = 0 : si32} : memref<48xi8>, vector<32xi8>
// CHECK : %[[T1:.*]] = aievec.upd {{.*}}[%[[C32:.*]]] {index = 0 : i8, offset = 0 : si32} : memref<48xi8>, vector<32xi8>
// CHECK : %[[T2:.*]] = aievec.shift %[[T0:.*]], %[[T1:.*]] {shift = 16 : i32} : vector<32xi8>, vector<32xi8>
// CHECK : %[[T3:.*]] = aievec.upd {{.*}}[%[[C64:.*]]] {index = 0 : i8, offset = 0 : si32} : memref<48xi8>, vector<32xi8>
// CHECK : %[[T4:.*]] = aievec.shift %[[T1:.*]], %[[T3:.*]] {shift = 2 : i32} : vector<32xi8>, vector<32xi8>
// CHECK : return %[[T2:.*]], %[[T4:.*]] : vector<32xi8>, vector<32xi8>
// CHECK: %[[C0:.*]] = arith.constant 0 : index
// CHECK: %[[V0B:.*]] = aievec.upd %{{.*}}[%[[C0]]] {index = 0 : i8, offset = 0 : si32} : memref<64xi32>, vector<32xi16>
// CHECK: %[[V0T:.*]] = aievec.upd %{{.*}}[%[[C0]]], %[[V0B]] {index = 1 : i8, offset = 256 : si32} : memref<64xi32>, vector<32xi16>
// CHECK: %[[V0ROT:.*]] = aievec.select %[[V0T]] {select = "0x11111111", xoffsets = "0x06040200", xoffsets_hi = "0x0e0c0a08", xsquare = "0x2103", xstart = "4",
// CHECK-SAME: yoffsets = "0x0503010f", yoffsets_hi = "0x0d0b0907", ysquare = "0x2103", ystart = "2"}
// CHECK-SAME: : vector<32xi16>, vector<32xi16>
// CHECK: %[[V0:.*]] = aievec.ext %[[V0ROT]] {index = 0 : i8} : vector<32xi16>, vector<16xi16>
// CHECK: %[[V1ROT:.*]] = aievec.select %[[V0T]] {select = "0", xoffsets = "0x06040200", xoffsets_hi = "0x0e0c0a08", xsquare = "0x3210", xstart = "6",
// CHECK-SAME: yoffsets = "0", yoffsets_hi = "0", ysquare = "0", ystart = "0"}
// CHECK-SAME: : vector<32xi16>, vector<32xi16>
// CHECK: %[[V1:.*]] = aievec.ext %[[V1ROT]] {index = 0 : i8} : vector<32xi16>, vector<16xi16>
// CHECK: return %[[V0]], %[[V1]] : vector<16xi16>, vector<16xi16>
func.func @unaligned_read(%m: memref<64xi32>) -> (vector<16xi16>, vector<16xi16>) {
%c0_i32 = arith.constant 0 : i32
%c3 = arith.constant 3 : index
%c6 = arith.constant 6 : index
%0 = vector.transfer_read %m[%c3], %c0_i32 : memref<64xi32>, vector<16xi16>
%1 = vector.transfer_read %m[%c6], %c0_i32 : memref<64xi32>, vector<16xi16>
return %0, %1 : vector<16xi16>, vector<16xi16>
}
43 changes: 43 additions & 0 deletions test/Integration/Dialect/AIEVec/v1_unaligned_read/i16/helplib.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
#include <cstdint>
#include <cstdio>

template <int nlanes, typename elemtype, typename vtype> void printv(vtype v) {
elemtype buff[nlanes];
*(vtype *)(buff) = v;
printf("vector<%dxi%d>[", nlanes, sizeof(elemtype) * 8);
for (int i = 0; i < nlanes - 1; ++i)
printf("%d, ", buff[i]);
printf("%d]\n", buff[nlanes - 1]);
}

void printv16xi32(v16int32 v) { printv<16, int32_t>(v); }

void printv8xi32(v8int32 v) { printv<8, int32_t>(v); }

void printv32xi16(v32int16 v) { printv<32, int16_t>(v); }

void printv16xi16(v16int16 v) { printv<16, int16_t>(v); }

void printv32xi8(v32int8 v) { printv<32, int8_t>(v); }

alignas(32) int32_t buff_i32[64];
alignas(32) int16_t buff_i16[64];
alignas(32) int8_t buff_i8[64];

int32_t *loadA64xi32() {
for (int i = 0; i < 64; ++i)
buff_i32[i] = i;
return buff_i32;
}

int16_t *loadA64xi16() {
for (int i = 0; i < 64; ++i)
buff_i16[i] = i;
return buff_i16;
}

int8_t *loadA64xi8() {
for (int i = 0; i < 64; ++i)
buff_i8[i] = i;
return buff_i8;
}
81 changes: 81 additions & 0 deletions test/Integration/Dialect/AIEVec/v1_unaligned_read/i16/kernel.mlir
Original file line number Diff line number Diff line change
@@ -0,0 +1,81 @@
// REQUIRES: valid_xchess_license
// RUN: aie-opt %s -convert-vector-to-aievec | aie-translate -aievec-to-cpp -o kernel.tmp.cc
// RUN: echo "#include <cstdint>" > kernel.cc && cat kernel.tmp.cc >> kernel.cc
// RUN: xchesscc_wrapper aie -f -g +s +w work +o work -I%S -I. kernel.cc %S/helplib.cc %S/main.cc
// RUN: xca_udm_dbg -qf -T -P %aietools/data/versal_prod/lib -t "%S/../../profiling.tcl ./work/a.out" | FileCheck %s

func.func private @printv16xi16(%v : vector<16xi16>)
func.func private @loadA64xi16() -> memref<64xi16>

#map6 = affine_map<(d0) -> (d0 + 6)>
#map7 = affine_map<(d0) -> (d0 + 7)>
#map8 = affine_map<(d0) -> (d0 + 8)>
#map9 = affine_map<(d0) -> (d0 + 9)>
#map10 = affine_map<(d0) -> (d0 + 10)>

func.func @entry() -> i32 {
%c0_i32 = arith.constant 0 : i32
%c0_i16 = arith.constant 0 : i16
%c0 = arith.constant 0 : index
%c1 = arith.constant 1 : index
%c2 = arith.constant 2 : index
%c3 = arith.constant 3 : index
%c4 = arith.constant 4 : index
%c5 = arith.constant 5 : index
%c6 = arith.constant 6 : index
%c7 = arith.constant 7 : index
%c8 = arith.constant 8 : index
%c9 = arith.constant 9 : index
%c10 = arith.constant 10 : index
%c11 = arith.constant 11 : index
%c12 = arith.constant 12 : index
%c13 = arith.constant 13 : index
%c14 = arith.constant 14 : index
%c15 = arith.constant 15 : index

%buffi16 = func.call @loadA64xi16() : () -> (memref<64xi16>)
%v16 = vector.transfer_read %buffi16[%c0], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%v16) : (vector<16xi16>) -> ()

%1 = vector.transfer_read %buffi16[%c1], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%1) : (vector<16xi16>) -> ()
%2 = vector.transfer_read %buffi16[%c2], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%2) : (vector<16xi16>) -> ()
%3 = vector.transfer_read %buffi16[%c3], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%3) : (vector<16xi16>) -> ()
%4 = vector.transfer_read %buffi16[%c4], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%4) : (vector<16xi16>) -> ()
%5 = vector.transfer_read %buffi16[%c5], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%5) : (vector<16xi16>) -> ()

%i6 = affine.apply #map6(%c0)
%6 = vector.transfer_read %buffi16[%i6], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%6) : (vector<16xi16>) -> ()
%i7 = affine.apply #map7(%c0)
%7 = vector.transfer_read %buffi16[%i7], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%7) : (vector<16xi16>) -> ()
%i8 = affine.apply #map8(%c0)
%8 = vector.transfer_read %buffi16[%i8], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%8) : (vector<16xi16>) -> ()
%i9 = affine.apply #map9(%c0)
%9 = vector.transfer_read %buffi16[%i9], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%9) : (vector<16xi16>) -> ()
%i10 = affine.apply #map10(%c0)
%10 = vector.transfer_read %buffi16[%i10], %c0_i16 : memref<64xi16>, vector<16xi16>
func.call @printv16xi16(%10) : (vector<16xi16>) -> ()

return %c0_i32 : i32
}

// CHECK-LABEL: vector<16xi16>[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
// CHECK-LABEL: vector<16xi16>[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
// CHECK-LABEL: vector<16xi16>[2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
// CHECK-LABEL: vector<16xi16>[3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
// CHECK-LABEL: vector<16xi16>[4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
// CHECK-LABEL: vector<16xi16>[5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
// CHECK-LABEL: vector<16xi16>[6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
// CHECK-LABEL: vector<16xi16>[7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
// CHECK-LABEL: vector<16xi16>[8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
// CHECK-LABEL: vector<16xi16>[9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
// CHECK-LABEL: vector<16xi16>[10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
// CHECK-LABEL: SUCCESS
11 changes: 11 additions & 0 deletions test/Integration/Dialect/AIEVec/v1_unaligned_read/i16/main.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
#include <cstdio>

int entry(void);

int main(void) {
int r = entry();
if (r)
printf("ERROR: %d", r);
printf("SUCCESS");
return r;
}
43 changes: 43 additions & 0 deletions test/Integration/Dialect/AIEVec/v1_unaligned_read/i32/helplib.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
#include <cstdint>
#include <cstdio>

template <int nlanes, typename elemtype, typename vtype> void printv(vtype v) {
elemtype buff[nlanes];
*(vtype *)(buff) = v;
printf("vector<%dxi%d>[", nlanes, sizeof(elemtype) * 8);
for (int i = 0; i < nlanes - 1; ++i)
printf("%d, ", buff[i]);
printf("%d]\n", buff[nlanes - 1]);
}

void printv16xi32(v16int32 v) { printv<16, int32_t>(v); }

void printv8xi32(v8int32 v) { printv<8, int32_t>(v); }

void printv32xi16(v32int16 v) { printv<32, int16_t>(v); }

void printv16xi16(v16int16 v) { printv<16, int16_t>(v); }

void printv32xi8(v32int8 v) { printv<32, int8_t>(v); }

alignas(32) int32_t buff_i32[64];
alignas(32) int16_t buff_i16[64];
alignas(32) int8_t buff_i8[64];

int32_t *loadA64xi32() {
for (int i = 0; i < 64; ++i)
buff_i32[i] = i;
return buff_i32;
}

int16_t *loadA64xi16() {
for (int i = 0; i < 64; ++i)
buff_i16[i] = i;
return buff_i16;
}

int8_t *loadA64xi8() {
for (int i = 0; i < 64; ++i)
buff_i8[i] = i;
return buff_i8;
}
35 changes: 35 additions & 0 deletions test/Integration/Dialect/AIEVec/v1_unaligned_read/i32/kernel.mlir
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
// REQUIRES: valid_xchess_license
// RUN: aie-opt %s -convert-vector-to-aievec | aie-translate -aievec-to-cpp -o kernel.tmp.cc
// RUN: echo "#include <cstdint>" > kernel.cc && cat kernel.tmp.cc >> kernel.cc
// RUN: xchesscc_wrapper aie -f -g +s +w work +o work -I%S -I. kernel.cc %S/helplib.cc %S/main.cc
// RUN: xca_udm_dbg -qf -T -P %aietools/data/versal_prod/lib -t "%S/../../profiling.tcl ./work/a.out" | FileCheck %s

func.func private @printv8xi32(%v : vector<8xi32>)
func.func private @loadA64xi32() -> memref<64xi32>

#map6 = affine_map<(d0) -> (d0 + 6)>

func.func @entry() -> i32 {
%c0_i32 = arith.constant 0 : i32
%c0 = arith.constant 0 : index
%c5 = arith.constant 5 : index

%buffi32 = func.call @loadA64xi32() : () -> (memref<64xi32>)

%v0 = vector.transfer_read %buffi32[%c0], %c0_i32 : memref<64xi32>, vector<8xi32>
func.call @printv8xi32(%v0) : (vector<8xi32>) -> ()

%v5 = vector.transfer_read %buffi32[%c5], %c0_i32 : memref<64xi32>, vector<8xi32>
func.call @printv8xi32(%v5) : (vector<8xi32>) -> ()

%idx6 = affine.apply #map6(%c0)
%v6 = vector.transfer_read %buffi32[%idx6], %c0_i32 : memref<64xi32>, vector<8xi32>
func.call @printv8xi32(%v6) : (vector<8xi32>) -> ()

return %c0_i32 : i32
}

// CHECK-LABEL: vector<8xi32>[0, 1, 2, 3, 4, 5, 6, 7]
// CHECK-LABEL: vector<8xi32>[5, 6, 7, 8, 9, 10, 11, 12]
// CHECK-LABEL: vector<8xi32>[6, 7, 8, 9, 10, 11, 12, 13]
// CHECK-LABEL: SUCCESS
11 changes: 11 additions & 0 deletions test/Integration/Dialect/AIEVec/v1_unaligned_read/i32/main.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
#include <cstdio>

int entry(void);

int main(void) {
int r = entry();
if (r)
printf("ERROR: %d", r);
printf("SUCCESS");
return r;
}

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